This example is a RISC CPU, very handy tested

RISC_CPU\accum.v
........\adr.v
........\alu.v
........\clk_gen.v
........\counter.v
........\cpu.v
........\datactl.v
........\machine.v
........\machinectl.v
........\register.v
........\tool_new.rar
........\Verilog硬件描述语言cpu设计实例.pdf
RISC_CPU

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