Complete engineering documents, based on actel s A3P250 development board, the project contains bench file for easy simulation

A3P250_Prj
..........\A3P250_Prj.prjx
..........\component
..........\.........\work
..........\.........\....\DESIGN_FIRMWARE
..........\.........\....\...............\DESIGN_FIRMWARE.cxf
..........\.........\....\...............\DESIGN_FIRMWARE.sdb
..........\.........\....\DESIGN_IO
..........\.........\....\.........\DESIGN_IO.cxf
..........\.........\....\.........\DESIGN_IO.sdb
..........\.........\....\test
..........\.........\....\....\datasheet.xsl
..........\.........\....\....\test.cxf
..........\.........\....\....\test.sdb
..........\.........\....\....\test_DataSheet.xml
..........\constraint
..........\coreconsole
..........\designer
..........\........\CheckBoard
..........\........\..........\export
..........\........\impl1
..........\........\.....\CheckBoard.adb
..........\........\.....\CheckBoard.dtf
..........\........\.....\..............\verify.log
..........\........\.....\CheckBoard.ide_des
..........\........\.....\CheckBoard.pdb
..........\........\.....\CheckBoard.pdb.depends
..........\........\.....\CheckBoard.tcl
..........\........\.....\CheckBoard_compile_log.rpt
..........\........\.....\CheckBoard_compile_report.txt
..........\........\.....\CheckBoard_fp
..........\........\.....\.............\$$FlashPro_40834.L$$
..........\........\.....\.............\CheckBoard.pro
..........\........\.....\.............\CheckBoard.tcl
..........\........\.....\.............\CheckBoard_program.log
..........\........\.....\.............\projectData
..........\........\.....\.............\...........\CheckBoard.pdb
..........\........\.....\CheckBoard_fp.tcl
..........\........\.....\CheckBoard_globalnet_report.txt
..........\........\.....\CheckBoard_globalusage_report.txt
..........\........\.....\CheckBoard_iobank_report.txt
..........\........\.....\CheckBoard_maxdelay_timing_report.txt
..........\........\.....\CheckBoard_maxdelay_timingviolations_report.txt
..........\........\.....\CheckBoard_mindelay_timing_report.txt
..........\........\.....\CheckBoard_mindelay_timingviolations_report.txt
..........\........\.....\CheckBoard_place_and_route_report.txt
..........\........\.....\CheckBoard_placeroute_log.rpt
..........\........\.....\CheckBoard_prgdata_log.rpt
..........\........\.....\CheckBoard_verifytiming_log.rpt
..........\........\.....\ada03412-1.tmp
..........\........\.....\run_designer_tool.log
..........\........\.....\run_designer_tool.tcl
..........\........\.....\simulation
..........\........\.....\test.adb
..........\........\.....\test.ide_des
..........\........\.....\test.tcl
..........\........\.....\test_compile_log.rpt
..........\........\.....\test_compile_report.txt
..........\firmware
..........\hdl
..........\...\CheckBoard.v
..........\phy_synthesis
..........\simulation
..........\..........\modelsim.ini
..........\..........\modelsim.ini.sav
..........\smartgen
..........\........\DESIGN_FIRMWARE_work.ixf
..........\........\DESIGN_IO_work.ixf
..........\........\pll80M
..........\........\......\pll80M.cxf
..........\........\......\pll80M.gen
..........\........\......\pll80M.log
..........\........\......\pll80M.v
..........\........\pll80M_work.ixf
..........\........\smartgen.aws
..........\........\test_work.ixf
..........\stimulus
..........\synthesis
..........\.........\.recordref_modgen
..........\.........\CheckBoard.areasrr
..........\.........\CheckBoard.edn
..........\.........\CheckBoard.fse
..........\.........\CheckBoard.htm
..........\.........\CheckBoard.map
..........\.........\CheckBoard.pdc
..........\.........\CheckBoard.sap
..........\.........\CheckBoard.sdf
..........\.........\CheckBoard.so
..........\.........\CheckBoard.srd
..........\.........\CheckBoard.srm
..........\.........\CheckBoard.srr
..........\.........\CheckBoard.srs
..........\.........\CheckBoard_scck.rpt
..........\.........\CheckBoard_sdc.sdc
..........\.........\CheckBoard_syn.bak
..........\.........\CheckBoard_syn.prj
..........\.........\CheckBoard_syn.tcl
..........\.........\backup
..........\.........\......\CheckBoard.srr
..........\.........\......\test

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