Powerline Communication FSK modulation frequency hopping technology, FPGA realization

FSK_DEMOUDULATION\.untf
.................\3_14_72k_in_10000000.mcs
.................\3_14_72k_in_10000000.prm
.................\3_14_72k_in_10000000.sig
.................\3_17_1426_in.mcs
.................\3_17_1426_in.prm
.................\3_17_1426_in.sig
.................\3_19_8freq.mcs
.................\3_19_8freq.prm
.................\3_19_8freq.sig
.................\3_19_clk1p2k_in.mcs
.................\3_19_clk1p2k_in.prm
.................\3_19_clk1p2k_in.sig
.................\3_6_72k_in.mcs
.................\3_6_72k_in.prm
.................\3_6_72k_in.sig
.................\3_6_72k_in_10000000.mcs
.................\3_6_72k_in_10000000.prm
.................\3_6_72k_in_10000000.sig
.................\4_27_fsk_jietiao.mcs
.................\4_27_fsk_jietiao.prm
.................\4_27_fsk_jietiao.sig
.................\4_5_200_270k_9203_1p2k_in.mcs
.................\4_5_200_270k_9203_1p2k_in.prm
.................\4_5_200_270k_9203_1p2k_in.sig
.................\4_5_24m_tb.vhd
.................\4_5_24m_tb_vhd.fdo
.................\4_5_24m_tb_vhd.udo
.................\531_270k_jietiao.mcs
.................\531_270k_jietiao.prm
.................\531_270k_jietiao.sig
.................\5_7_jietiao.mcs
.................\5_7_jietiao.prm
.................\5_7_jietiao.sig
.................\ad_con.vhd
.................\automake.log
.................\bitgen.ut
.................\clk_48m.vhd
.................\clk_4p8m.vhd
.................\clock_manage.vhd
.................\clock_manage_summary.html
.................\clock_manage_tv.ant
.................\clock_manage_tv.fdo
.................\clock_manage_tv.jhd
.................\clock_manage_tv.tbw
.................\clock_manage_tv.udo
.................\clock_manage_tv.vhw
.................\clock_manage_tv.xwv
.................\clock_manage_tv.xwv_bak
.................\clock_manage_tv_bencher.prj
.................\coef.coe
.................\COEF_BUFFER.mif
.................\core.tpl
.................\coregen.log
.................\cosine_lpf.asy
.................\cosine_lpf.edn
.................\cosine_lpf.mif
.................\cosine_lpf.sym
.................\cosine_lpf.v
.................\cosine_lpf.veo
.................\cosine_lpf.vho
.................\cosine_lpf.xco
.................\cosine_lpf_flist.txt
.................\cosine_lpf_readme.txt
.................\danwen_filter.coe
.................\danwen_gen.vhd.bak
.................\danwen_gen_summary.html
.................\dds.asy
.................\dds.edn
.................\dds.ngo
.................\dds.sym
.................\dds.v
.................\dds.veo
.................\dds.vhd
.................\dds.vho
.................\DDS.xco
.................\DDS60.asy
.................\dds60.edn
.................\dds60.ngo
.................\dds60.sym
.................\dds60.v
.................\dds60.veo
.................\dds60.vhd
.................\dds60.vho
.................\DDS60.xco
.................\dds60_flist.txt
.................\dds60_readme.txt
.................\dds60_SINCOS_TABLE_TRIG_ROM.mif
.................\DDS72.asy
.................\dds72.edn
.................\dds72.sym
.................\dds72.v
.................\dds72.veo
.................\dds72.vhd
.................\dds72.vho
.................\DDS72.xco
.................\dds72_flist.txt
.................\dds72_readme.txt
.................\dds72_SINCOS_TABLE_TRIG_ROM.mif
.................\dds_flist.txt

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