Based on FPGA v5 of ddr2-sdram controller design verilog

ddr2_v5\coregen.cgp
.......\mig_v3_5_readme.txt
.......\_xmsgs\pn_parser.xmsgs
.......\mig_v3_5\docs\adr_cntrl_timing.xls
.......\........\....\read_data_timing.xls
.......\........\....\ug086.pdf
.......\........\....\write_data_timing.xls
.......\........\example_design\datasheet.txt
.......\........\..............\log.txt
.......\........\..............\mig.prj
.......\........\..............\par\compatible_ucf\xc5vsx50t_ff1136.ucf
.......\........\..............\...\create_ise.bat
.......\........\..............\...\icon4_cg.xco
.......\........\..............\...\ise_flow.bat
.......\........\..............\...\makeproj.bat
.......\........\..............\...\mem_interface_top.ut
.......\........\..............\...\mig_v3_5.cdc
.......\........\..............\...\mig_v3_5.ucf
.......\........\..............\...\readme.txt
.......\........\..............\...\rem_files.bat
.......\........\..............\...\set_ise_prop.tcl
.......\........\..............\...\vio_async_in100_cg.xco
.......\........\..............\...\vio_async_in192_cg.xco
.......\........\..............\...\vio_async_in96_cg.xco
.......\........\..............\...\vio_sync_out32_cg.xco
.......\........\..............\...\xst_run.txt
.......\........\..............\rtl\ddr2_chipscope.v
.......\........\..............\...\ddr2_ctrl.v
.......\........\..............\...\ddr2_idelay_ctrl.v
.......\........\..............\...\ddr2_infrastructure.v
.......\........\..............\...\ddr2_mem_if_top.v
.......\........\..............\...\ddr2_phy_calib.v
.......\........\..............\...\ddr2_phy_ctl_io.v
.......\........\..............\...\ddr2_phy_dm_iob.v
.......\........\..............\...\ddr2_phy_dq_iob.v
.......\........\..............\...\ddr2_phy_dqs_iob.v
.......\........\..............\...\ddr2_phy_init.v
.......\........\..............\...\ddr2_phy_io.v
.......\........\..............\...\ddr2_phy_top.v
.......\........\..............\...\ddr2_phy_write.v
.......\........\..............\...\ddr2_tb_test_addr_gen.v
.......\........\..............\...\ddr2_tb_test_cmp.v
.......\........\..............\...\ddr2_tb_test_data_gen.v
.......\........\..............\...\ddr2_tb_test_gen.v
.......\........\..............\...\ddr2_tb_top.v
.......\........\..............\...\ddr2_top.v
.......\........\..............\...\ddr2_usr_addr_fifo.v
.......\........\..............\...\ddr2_usr_rd.v
.......\........\..............\...\ddr2_usr_top.v
.......\........\..............\...\ddr2_usr_wr.v
.......\........\..............\...\mig_v3_5.v
.......\........\..............\sim\ddr2_model.v
.......\........\..............\...\ddr2_model_parameters.vh
.......\........\..............\...\sim.do
.......\........\..............\...\sim_tb_top.v
.......\........\..............\...\wiredly.v
.......\........\..............\.ynth\mem_interface_top_synp.sdc
.......\........\..............\.....\mig_v3_5.lso
.......\........\..............\.....\mig_v3_5.prj
.......\........\..............\.....\script_synp.tcl
.......\........\..............\.im_lc\ddr2_chipscope.v
.......\........\..............\......\ddr2_ctrl.v
.......\........\..............\......\ddr2_idelay_ctrl.v
.......\........\..............\......\ddr2_infrastructure.v
.......\........\..............\......\ddr2_mem_if_top.v
.......\........\..............\......\ddr2_phy_calib.v
.......\........\..............\......\ddr2_phy_ctl_io.v
.......\........\..............\......\ddr2_phy_dm_iob.v
.......\........\..............\......\ddr2_phy_dq_iob.v
.......\........\..............\......\ddr2_phy_dqs_iob.v
.......\........\..............\......\ddr2_phy_init.v
.......\........\..............\......\ddr2_phy_io.v
.......\........\..............\......\ddr2_phy_top.v
.......\........\..............\......\ddr2_phy_write.v
.......\........\..............\......\ddr2_tb_test_addr_gen.v
.......\........\..............\......\ddr2_tb_test_cmp.v
.......\........\..............\......\ddr2_tb_test_data_gen.v
.......\........\..............\......\ddr2_tb_test_gen.v
.......\........\..............\......\ddr2_t

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