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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-05-31
  • Size : 150kb
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Introduction - If you have any usage issues, please Google them yourself
the fpga vga programming, based on verilog language, learn
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Chapter8 Sample
...............\vga
...............\...\__projnav
...............\...\.........\coregen.rsp
...............\...\.........\runXst_tcl.rsp
...............\...\.........\vga.gfl
...............\...\.........\vga_enh_top.xst
...............\...\.........\vga_flowplus.gfl
...............\...\.........\xst_sprjTOstx_tcl.rsp
...............\...\__projnav.log
...............\...\automake.log
...............\...\coregen.log
...............\...\coregen.prj
...............\...\generic_dpram.v
...............\...\generic_spram.v
...............\...\prjname.lso
...............\...\sync_check.v
...............\...\test_bench_top.v
...............\...\test_bench_top.v.bak
...............\...\tests.v
...............\...\tests.v.bak
...............\...\timescale.v
...............\...\vga.dhp
...............\...\vga.npl
...............\...\vga_clkgen.v
...............\...\vga_colproc.v
...............\...\vga_csm_pb.v
...............\...\vga_cur_cregs.v
...............\...\vga_curproc.v
...............\...\vga_defines.v
...............\...\vga_defines.v.bak
...............\...\vga_enh_top.cmd_log
...............\...\vga_enh_top.lso
...............\...\vga_enh_top.prj
...............\...\vga_enh_top.stx
...............\...\vga_enh_top.syr
...............\...\vga_enh_top.v
...............\...\vga_enh_top_vhdl.prj
...............\...\vga_fifo.v
...............\...\vga_fifo_dc.v
...............\...\vga_pgen.v
...............\...\vga_tgen.v
...............\...\vga_vtim.v
...............\...\vga_wb_master.v
...............\...\vga_wb_master.v.bak
...............\...\vga_wb_slave.v
...............\...\vga_wb_slave.v.bak
...............\...\wb_b3_check.v
...............\...\wb_b3_check.v.bak
...............\...\wb_mast_model.v
...............\...\wb_model_defines.v
...............\...\wb_model_defines.v.bak
...............\...\wb_slv_model.v
...............\...\wb_slv_model.v.bak
...............\...\xst
...............\...\...\work
...............\...\...\....\hdllib.ref
...............\...\...\....\vlg04
...............\...\...\....\.....\vga_wb_slave.bin
...............\...\...\....\vlg05
...............\...\...\....\.....\vga_wb_master.bin
...............\...\...\....\vlg07
...............\...\...\....\.....\vga_fifo_dc.bin
...............\...\...\....\.....\vga_pgen.bin
...............\...\...\....\vlg34
...............\...\...\....\.....\generic_dpram.bin
...............\...\...\....\vlg4D
...............\...\...\....\.....\vga_csm_pb.bin
...............\...\...\....\.....\vga_vtim.bin
...............\...\...\....\vlg53
...............\...\...\....\.....\generic_spram.bin
...............\...\...\....\vlg59
...............\...\...\....\.....\vga_clkgen.bin
...............\...\...\....\vlg5D
...............\...\...\....\.....\vga_fifo.bin
...............\...\...\....\vlg5F
...............\...\...\....\.....\vga_colproc.bin
...............\...\...\....\vlg6A
...............\...\...\....\.....\vga_enh_top.bin
...............\...\...\....\vlg7B
...............\...\...\....\.....\vga_tgen.bin
...............\使用说明.txt
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