FPGA boundary scan when the TAP controller, this is a project file with modelsim simulation

tapcontroller
.............\tapcontroller.cr.mti
.............\tapcontroller.mpf
.............\tapcontroller.v
.............\tapcontroller.v.bak
.............\tapcontroller.vhd.bak
.............\test.v
.............\test.v.bak
.............\vsim.wlf
.............\wave.do
.............\work
.............\....\_info
.............\....\_temp
.............\....\_vmake
.............\....\tapcontroller
.............\....\.............\_primary.dat
.............\....\.............\_primary.dbs
.............\....\.............\_primary.vhd
.............\....\.............\verilog.prw
.............\....\.............\verilog.psm
.............\....\test
.............\....\....\_primary.dat
.............\....\....\_primary.dbs
.............\....\....\_primary.vhd
.............\....\....\verilog.prw
.............\....\....\verilog.psm

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