Digital clock VHDL realization, minutes and seconds can be adjusted in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Altera' s Cyclone3 EP3C8T1

hsk4571_clock\db
.............\..\altsyncram_38p3.tdf
.............\..\altsyncram_v7p3.tdf
.............\..\cmpr_efc.tdf
.............\..\cmpr_hfc.tdf
.............\..\cmpr_ifc.tdf
.............\..\cntr_5fi.tdf
.............\..\cntr_6fi.tdf
.............\..\cntr_8fi.tdf
.............\..\cntr_95j.tdf
.............\..\cntr_p1j.tdf
.............\..\decode_4uf.tdf
.............\..\hsk4571_clock.archive.qmsg
.............\..\hsk4571_clock.asm.qmsg
.............\..\hsk4571_clock.asm_labs.ddb
.............\..\hsk4571_clock.cbx.xml
.............\..\hsk4571_clock.cmp.bpm
.............\..\hsk4571_clock.cmp.cdb
.............\..\hsk4571_clock.cmp.ecobp
.............\..\hsk4571_clock.cmp.hdb
.............\..\hsk4571_clock.cmp.kpt
.............\..\hsk4571_clock.cmp.logdb
.............\..\hsk4571_clock.cmp.rdb
.............\..\hsk4571_clock.cmp_merge.kpt
.............\..\hsk4571_clock.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.............\..\hsk4571_clock.cuda_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
.............\..\hsk4571_clock.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.............\..\hsk4571_clock.db_info
.............\..\hsk4571_clock.eco.cdb
.............\..\hsk4571_clock.eds_overflow
.............\..\hsk4571_clock.fit.qmsg
.............\..\hsk4571_clock.fnsim.hdb
.............\..\hsk4571_clock.fnsim.qmsg
.............\..\hsk4571_clock.hier_info
.............\..\hsk4571_clock.hif
.............\..\hsk4571_clock.lpc.html
.............\..\hsk4571_clock.lpc.rdb
.............\..\hsk4571_clock.lpc.txt
.............\..\hsk4571_clock.map.bpm
.............\..\hsk4571_clock.map.cdb
.............\..\hsk4571_clock.map.ecobp
.............\..\hsk4571_clock.map.hdb
.............\..\hsk4571_clock.map.kpt
.............\..\hsk4571_clock.map.logdb
.............\..\hsk4571_clock.map.qmsg
.............\..\hsk4571_clock.map_bb.cdb
.............\..\hsk4571_clock.map_bb.hdb
.............\..\hsk4571_clock.map_bb.logdb
.............\..\hsk4571_clock.pre_map.cdb
.............\..\hsk4571_clock.pre_map.hdb
.............\..\hsk4571_clock.rtlv.hdb
.............\..\hsk4571_clock.rtlv_sg.cdb
.............\..\hsk4571_clock.rtlv_sg_swap.cdb
.............\..\hsk4571_clock.sgdiff.cdb
.............\..\hsk4571_clock.sgdiff.hdb
.............\..\hsk4571_clock.sim.hdb
.............\..\hsk4571_clock.sim.qmsg
.............\..\hsk4571_clock.sim.rdb
.............\..\hsk4571_clock.sim_ori.vwf
.............\..\hsk4571_clock.simfam
.............\..\hsk4571_clock.sld_design_entry.sci
.............\..\hsk4571_clock.sld_design_entry_dsc.sci
.............\..\hsk4571_clock.sta.qmsg
.............\..\hsk4571_clock.sta.rdb
.............\..\hsk4571_clock.sta_cmp.7_slow_1200mv_85c.tdb
.............\..\hsk4571_clock.syn_hier_info
.............\..\hsk4571_clock.tis_db_list.ddb
.............\..\hsk4571_clock.tiscmp.fast_1200mv_0c.ddb
.............\..\hsk4571_clock.tiscmp.slow_1200mv_0c.ddb
.............\..\hsk4571_clock.tiscmp.slow_1200mv_85c.ddb
.............\..\hsk4571_clock_global_asgn_op.abo
.............\..\mux_1sc.tdf
.............\..\mux_jrc.tdf
.............\..\mux_jtc.tdf
.............\..\prev_cmp_hsk4571_clock.archive.qmsg
.............\..\prev_cmp_hsk4571_clock.asm.qmsg
.............\..\prev_cmp_hsk4571_clock.fit.qmsg
.............\..\prev_cmp_hsk4571_clock.map.qmsg
.............\..\prev_cmp_hsk4571_clock.qmsg
.............\..\prev_cmp_hsk4571_clock.sim.qmsg
.............\..\prev_cmp_hsk4571_clock.sta.qmsg
.............\..\wed.wsf
.............\hsk4571_clock.archive.rpt
.............\hsk4571_clock.asm.rpt
.............\hsk4571_clock.bdf
.............\hsk4571_clock.done
.............\hsk4571_clock.fit.rpt
.............\hsk4571_clock.fit.smsg
.............\hsk4571_clock.fit.summary
.............\hsk4571_clock.flow.rpt
.............\hsk4571_clock.jdi
.............\hsk4571_clock.map.rpt
.............\hsk4571_clock.map.summary
.............\hsk4571_clock.pin
.............\hsk4571_clock.qar
.............\hsk4571_clock.qarlog
.............\hsk4571_clock.qpf
.............\hsk4571_clock.qsf
.............\hsk4571_clock.qws
.............\hsk4571_clock.sim.rpt

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