FPGA Verilog HDL language construct serial receive a detailed program design

UartRecv\stp1.stp
........\UartRecv.asm.rpt
........\UartRecv.cdf
........\UartRecv.done
........\UartRecv.fit.rpt
........\UartRecv.fit.smsg
........\UartRecv.fit.summary
........\UartRecv.flow.rpt
........\UartRecv.jdi
........\UartRecv.map.rpt
........\UartRecv.map.summary
........\UartRecv.pin
........\UartRecv.pof
........\UartRecv.qpf
........\UartRecv.qpf.bak
........\UartRecv.qsf
........\UartRecv.qsf.bak
........\UartRecv.qsf~
........\UartRecv.qws
........\UartRecv.sof
........\UartRecv.sta.rpt
........\UartRecv.sta.summary
........\UartRecv.tan.rpt
........\UartRecv.tan.summary
........\UartRecv_assignment_defaults.qdf
........\详细设计方案\ASCII码对照表.doc
........\............\详细设计方案_UartRecv.doc
........\RTL\UartRecv.jpg
........\...\UartRecv.v
........\...\UartRecv.v.bak
........\incremental_db\README
........\..............\compiled_partitions\UartRecv.autoh_e4eb1.map.cdb
........\..............\...................\UartRecv.autoh_e4eb1.map.dpi
........\..............\...................\UartRecv.autoh_e4eb1.map.hdb
........\..............\...................\UartRecv.autoh_e4eb1.map.kpt
........\..............\...................\UartRecv.autoh_e4eb1.map.logdb
........\..............\...................\UartRecv.autos_3e921.map.cdb
........\..............\...................\UartRecv.autos_3e921.map.dpi
........\..............\...................\UartRecv.autos_3e921.map.hdb
........\..............\...................\UartRecv.autos_3e921.map.kpt
........\..............\...................\UartRecv.autos_3e921.map.logdb
........\..............\...................\UartRecv.db_info
........\..............\...................\UartRecv.root_partition.cmp.cdb
........\..............\...................\UartRecv.root_partition.cmp.dfp
........\..............\...................\UartRecv.root_partition.cmp.hdb
........\..............\...................\UartRecv.root_partition.cmp.kpt
........\..............\...................\UartRecv.root_partition.cmp.logdb
........\..............\...................\UartRecv.root_partition.cmp.rcfdb
........\..............\...................\UartRecv.root_partition.map.cdb
........\..............\...................\UartRecv.root_partition.map.dpi
........\..............\...................\UartRecv.root_partition.map.hbdb.cdb
........\..............\...................\UartRecv.root_partition.map.hbdb.hb_info
........\..............\...................\UartRecv.root_partition.map.hbdb.hdb
........\..............\...................\UartRecv.root_partition.map.hbdb.sig
........\..............\...................\UartRecv.root_partition.map.hdb
........\..............\...................\UartRecv.root_partition.map.kpt
........\db\altsyncram_2hq1.tdf
........\..\altsyncram_67p3.tdf
........\..\altsyncram_e7p3.tdf
........\..\altsyncram_g7p3.tdf
........\..\altsyncram_igq1.tdf
........\..\altsyncram_m7p3.tdf
........\..\altsyncram_qgq1.tdf
........\..\altsyncram_s024.tdf
........\..\altsyncram_sgq1.tdf
........\..\cmpr_ngc.tdf
........\..\cmpr_rgc.tdf
........\..\cntr_23j.tdf
........\..\cntr_8bi.tdf
........\..\cntr_abi.tdf
........\..\cntr_c4j.tdf
........\..\cntr_cgi.tdf
........\..\cntr_dbi.tdf
........\..\cntr_ebi.tdf
........\..\cntr_egi.tdf
........\..\cntr_g9j.tdf
........\..\cntr_hbi.tdf
........\..\cntr_uti.tdf
........\..\decode_aoi.tdf
........\..\decode_dvf.tdf
........\..\decode_rqf.tdf
........\..\logic_util_heursitic.dat
........\..\mux_9oc.tdf
........\..\mux_rsc.tdf
........\..\prev_cmp_UartRecv.asm.qmsg
........\..\prev_cmp_UartRecv.fit.qmsg
........\..\prev_cmp_UartRecv.map.qmsg
........\..\prev_cmp_UartRecv.qmsg
........\..\prev_cmp_UartRecv.tan.qmsg
........\..\UartRecv.amm.cdb
........\..\UartRecv.asm.qmsg
........\..\UartRecv.asm.rdb
........\..\UartRecv.asm_labs.ddb
........\..\UartRecv.cbx.xml
........\..\UartRecv.cmp.bpm
........\..\UartRecv.cmp.cdb
........\..\UartRecv.cmp.hdb
........\..\UartRecv.cmp.kpt
........\..\UartRecv.cmp.logdb
........\..\UartRecv.cmp.rdb

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