SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, DDR II code

Exp26_DDRII\.sopc_builder\install.ptf
...........\.............\install2.ptf
...........\.............\preferences.xml
...........\altmemddr_0.html
...........\altmemddr_0.ppf
...........\altmemddr_0.qip
...........\altmemddr_0.v
...........\altmemddr_0_advisor.ipa
...........\altmemddr_0_auk_ddr_hp_controller_wrapper.v
...........\altmemddr_0_controller_phy.v
...........\altmemddr_0_example_driver.v
...........\altmemddr_0_example_top.sdc
...........\altmemddr_0_example_top.v
...........\altmemddr_0_example_top.v.tmp
...........\altmemddr_0_example_top.v.tmp2
...........\altmemddr_0_example_top_1.v
...........\altmemddr_0_example_top_10.v
...........\altmemddr_0_example_top_11.v
...........\altmemddr_0_example_top_12.v
...........\altmemddr_0_example_top_13.v
...........\altmemddr_0_example_top_14.v
...........\altmemddr_0_example_top_15.v
...........\altmemddr_0_example_top_2.v
...........\altmemddr_0_example_top_3.v
...........\altmemddr_0_example_top_4.v
...........\altmemddr_0_example_top_5.v
...........\altmemddr_0_example_top_6.v
...........\altmemddr_0_example_top_7.v
...........\altmemddr_0_example_top_8.v
...........\altmemddr_0_example_top_9.v
...........\altmemddr_0_ex_lfsr8.v
...........\altmemddr_0_phy.html
...........\altmemddr_0_phy.qip
...........\altmemddr_0_phy.v
...........\altmemddr_0_phy_alt_mem_phy.v
...........\altmemddr_0_phy_alt_mem_phy_pll.ppf
...........\altmemddr_0_phy_alt_mem_phy_pll.qip
...........\altmemddr_0_phy_alt_mem_phy_pll.v
...........\altmemddr_0_phy_alt_mem_phy_pll.v_.bak
...........\altmemddr_0_phy_alt_mem_phy_pll_bb.v
...........\altmemddr_0_phy_alt_mem_phy_sequencer_wrapper.v
...........\altmemddr_0_phy_autodetectedpins.tcl
...........\altmemddr_0_phy_ddr_pins.tcl
...........\altmemddr_0_phy_ddr_timing.sdc
...........\altmemddr_0_phy_report_timing.tcl
...........\altmemddr_0_phy_simgen_init.txt
...........\altmemddr_0_phy_summary.csv
...........\altmemddr_0_pin_assignments.tcl
...........\altpllpll_0.ppf
...........\altpllpll_0.qip
...........\altpllpll_0.v
...........\altpllpll_0_bb.v
...........\altpllpll_0_wave0.jpg
...........\altpllpll_0_waveforms.html
...........\alt_mem_phy_defines.v
...........\alt_mem_phy_sequencer.vhd
...........\auk_ddr_hp_controller.ocp
...........\auk_ddr_hp_controller.vhd
...........\CIII_Demo.asm.rpt
...........\CIII_Demo.bdf
...........\CIII_Demo.done
...........\CIII_Demo.dpf
...........\CIII_Demo.drc.rpt
...........\CIII_Demo.fit.rpt
...........\CIII_Demo.fit.smsg
...........\CIII_Demo.fit.summary
...........\CIII_Demo.flow.rpt
...........\CIII_Demo.jdi
...........\CIII_Demo.map.rpt
...........\CIII_Demo.map.smsg
...........\CIII_Demo.map.summary
...........\CIII_Demo.pin
...........\CIII_Demo.qarlog
...........\CIII_Demo.qpf
...........\CIII_Demo.qsf
...........\CIII_Demo.qws
...........\CIII_Demo.sta.rpt
...........\CIII_Demo.sta.summary
...........\CIII_Demo_time_limited.cdf
...........\CIII_Demo_time_limited.sof
...........\cpu_0.ocp
...........\cpu_0.sdc
...........\cpu_0.v
...........\cpu_0_bht_ram.mif
...........\cpu_0_dc_tag_ram.mif
...........\cpu_0_ic_tag_ram.mif
...........\cpu_0_jtag_debug_module_sysclk.v
...........\cpu_0_jtag_debug_module_tck.v
...........\cpu_0_jtag_debug_module_wrapper.v
...........\cpu_0_mult_cell.v
...........\cpu_0_ociram_default_contents.mif
...........\cpu_0_oci_test_bench.v
...........\cpu_0_rf_ram_a.mif
...........\cpu_0_rf_ram_b.mif
...........\cpu_0_test_bench.v
...........\ddr2_pin_assignments.tcl
...........\ddr2_pin_assignments.tcl.bak
...........\incremental_db\compiled_partitions\CIII_Demo.nabbo_fd801ef9486a30386794de538b6d4a1.map.atm
...........\..............\...................\CIII_Demo.nabbo_fd801ef9486a30386794de538b6d4a1.map.hdbx
...........\..............\...................\CIII_Demo.nabbo_fd801ef9486a30386794de538b6d4a1.map.kpt

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