Based on multi-waveform signal generator cpld. Can produce a square wave, triangle wave, sine wave, sawtooth wave. Through a set of DIP switch frequency increases and decreases. Wherein the frequency of 100 ~ 1000hz discontinuous change.

FPGA_Function_v3\1024.mif
................\1024.mif.bak
................\Control.v
................\Control.v.bak
................\cpld_r.qip
................\cpld_r.v
................\cpld_r_bb.v
................\DAControl.v
................\DAControl.v.bak
................\db\add_sub_2ih.tdf
................\..\add_sub_6nh.tdf
................\..\add_sub_dch.tdf
................\..\add_sub_nlh.tdf
................\..\add_sub_sah.tdf
................\..\altsyncram_kc51.tdf
................\..\cmpr_2vb.tdf
................\..\cntr_m7j.tdf
................\..\DDSFPGA.cbx.xml
................\..\DDSFPGA.cmp.cdb
................\..\DDSFPGA.cmp.hdb
................\..\DDSFPGA.cmp.logdb
................\..\DDSFPGA.cmp.rdb
................\..\DDSFPGA.db_info
................\..\DDSFPGA.eco.cdb
................\..\DDSFPGA.fit.qmsg
................\..\DDSFPGA.hier_info
................\..\DDSFPGA.hif
................\..\DDSFPGA.lpc.html
................\..\DDSFPGA.lpc.rdb
................\..\DDSFPGA.lpc.txt
................\..\DDSFPGA.map.cdb
................\..\DDSFPGA.map.hdb
................\..\DDSFPGA.map.logdb
................\..\DDSFPGA.map.qmsg
................\..\DDSFPGA.pre_map.cdb
................\..\DDSFPGA.pre_map.hdb
................\..\DDSFPGA.rtlv.hdb
................\..\DDSFPGA.rtlv_sg.cdb
................\..\DDSFPGA.rtlv_sg_swap.cdb
................\..\DDSFPGA.sgdiff.cdb
................\..\DDSFPGA.sgdiff.hdb
................\..\DDSFPGA.sld_design_entry.sci
................\..\DDSFPGA.sld_design_entry_dsc.sci
................\..\DDSFPGA.smart_action.txt
................\..\DDSFPGA.syn_hier_info
................\..\DDSFPGA.tis_db_list.ddb
................\..\DDSFPGA.tmw_info
................\..\logic_util_heursitic.dat
................\..\prev_cmp_DDSFPGA.asm.qmsg
................\..\prev_cmp_DDSFPGA.eda.qmsg
................\..\prev_cmp_DDSFPGA.fit.qmsg
................\..\prev_cmp_DDSFPGA.map.qmsg
................\..\prev_cmp_DDSFPGA.qmsg
................\..\prev_cmp_DDSFPGA.tan.qmsg
................\DDSCPLD.hex
................\DDSFPGA.asm.rpt
................\DDSFPGA.cdf
................\DDSFPGA.done
................\DDSFPGA.dpf
................\DDSFPGA.eda.rpt
................\DDSFPGA.fit.rpt
................\DDSFPGA.fit.smsg
................\DDSFPGA.fit.summary
................\DDSFPGA.flow.rpt
................\DDSFPGA.map.rpt
................\DDSFPGA.map.smsg
................\DDSFPGA.map.summary
................\DDSFPGA.pin
................\DDSFPGA.pof
................\DDSFPGA.qpf
................\DDSFPGA.qsf
................\DDSFPGA.qws
................\DDSFPGA.sof
................\DDSFPGA.sta.rpt
................\DDSFPGA.sta.summary
................\DDSFPGA.tan.rpt
................\DDSFPGA.tan.summary
................\DDSFPGA.v
................\DDSFPGA.v.bak
................\DDSFPGA_assignment_defaults.qdf
................\DDSFPGA_nativelink_simulation.rpt
................\incremental_db\compiled_partitions\DDSFPGA.root_partition.cmp.dfp
................\..............\...................\DDSFPGA.root_partition.cmp.kpt
................\..............\...................\DDSFPGA.root_partition.cmp.logdb
................\..............\...................\DDSFPGA.root_partition.map.dpi
................\..............\...................\DDSFPGA.root_partition.map.kpt
................\..............\README
................\Mif1.mif
................\qmegawiz_errors_log.txt
................\romlookup.qip
................\romlookup2.qip
................\romlookup_wave0.jpg
................\simulation\modelsim\1024.mif
................\..........\........\1024.ver
................\..........\........\DA.bmp
................\..........\........\DAControl.v.bak
................\..........\........\DDSFPGA.sft
................\..........\........\DDSFPGA.vo
................\..........\........\DDSFPGA.vt
................\..........\........\DDSFPGA.vt.bak

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