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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-05-23
  • Size : 480kb
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  • Author :c*****
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Introduction - If you have any usage issues, please Google them yourself
FSM source –Next state calculation –Output calculation –State transition
Packet file list
(Preview for download)


db\logic_util_heursitic.dat
..\part1.asm.qmsg
..\part1.asm.rdb
..\part1.asm_labs.ddb
..\part1.cbx.xml
..\part1.cmp.bpm
..\part1.cmp.cdb
..\part1.cmp.hdb
..\part1.cmp.idb
..\part1.cmp.kpt
..\part1.cmp.logdb
..\part1.cmp.rdb
..\part1.cmp0.ddb
..\part1.cmp1.ddb
..\part1.cmp_merge.kpt
..\part1.db_info
..\part1.eda.qmsg
..\part1.fit.qmsg
..\part1.hier_info
..\part1.hif
..\part1.ipinfo
..\part1.lpc.html
..\part1.lpc.rdb
..\part1.lpc.txt
..\part1.map.bpm
..\part1.map.cdb
..\part1.map.hdb
..\part1.map.kpt
..\part1.map.logdb
..\part1.map.qmsg
..\part1.map.rdb
..\part1.map_bb.cdb
..\part1.map_bb.hdb
..\part1.map_bb.logdb
..\part1.pplq.rdb
..\part1.pre_map.cdb
..\part1.pre_map.hdb
..\part1.qns
..\part1.root_partition.map.reg_db.cdb
..\part1.routing.rdb
..\part1.rtlv.hdb
..\part1.rtlv_sg.cdb
..\part1.rtlv_sg_swap.cdb
..\part1.sas
..\part1.sgdiff.cdb
..\part1.sgdiff.hdb
..\part1.sld_design_entry.sci
..\part1.sld_design_entry_dsc.sci
..\part1.smart_action.txt
..\part1.sta.qmsg
..\part1.sta.rdb
..\part1.sta_cmp.6_slow.tdb
..\part1.syn_hier_info
..\part1.tis_db_list.ddb
..\part1.tmw_info
..\part1.vpr.ammdb
..\prev_cmp_part1.qmsg
incremental_db\compiled_partitions\part1.db_info
..............\...................\part1.root_partition.cmp.ammdb
..............\...................\part1.root_partition.cmp.cdb
..............\...................\part1.root_partition.cmp.dfp
..............\...................\part1.root_partition.cmp.hdb
..............\...................\part1.root_partition.cmp.kpt
..............\...................\part1.root_partition.cmp.logdb
..............\...................\part1.root_partition.cmp.rcfdb
..............\...................\part1.root_partition.map.cdb
..............\...................\part1.root_partition.map.dpi
..............\...................\part1.root_partition.map.hbdb.cdb
..............\...................\part1.root_partition.map.hbdb.hb_info
..............\...................\part1.root_partition.map.hbdb.hdb
..............\...................\part1.root_partition.map.hbdb.sig
..............\...................\part1.root_partition.map.hdb
..............\...................\part1.root_partition.map.kpt
..............\README
output_files\part1.asm.rpt
............\part1.done
............\part1.eda.rpt
............\part1.fit.rpt
............\part1.fit.smsg
............\part1.fit.summary
............\part1.flow.rpt
............\part1.jdi
............\part1.map.rpt
............\part1.map.summary
............\part1.pin
............\part1.pof
............\part1.sof
............\part1.sta.rpt
............\part1.sta.summary
simulation\modelsim\gate_work\@testbench\_primary.dat
..........\........\.........\..........\_primary.dbs
..........\........\.........\..........\_primary.vhd
..........\........\.........\..........\verilog.prw
..........\........\.........\..........\verilog.psm
..........\........\.........\_temp
..........\........\.........\part1\_primary.dat
..........\........\.........\.....\_primary.dbs
..........\........\.........\.....\_primary.vhd
..........\........\.........\.....\verilog.prw
..........\........\.........\.....\verilog.psm
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