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  • Update : 2013-05-19
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FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
Packet file list
(Preview for download)


prj_5\cores\coregen.cgc
.....\.....\coregen.cgp
.....\.....\MyFIFO_Block_Memory_v7_1\blk_mem_gen_v7_1_readme.txt
.....\.....\........................\doc\blk_mem_gen_ds512.pdf
.....\.....\........................\...\blk_mem_gen_v7_1_vinfo.html
.....\.....\........................\example_design\MyFIFO_Block_Memory_v7_1_exdes.ucf
.....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_exdes.vhd
.....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_exdes.xdc
.....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_prod.vhd
.....\.....\........................\implement\implement.bat
.....\.....\........................\.........\implement.sh
.....\.....\........................\.........\planAhead_ise.bat
.....\.....\........................\.........\planAhead_ise.sh
.....\.....\........................\.........\planAhead_ise.tcl
.....\.....\........................\.........\planAhead_rdn.bat
.....\.....\........................\.........\planAhead_rdn.sh
.....\.....\........................\.........\planAhead_rdn.tcl
.....\.....\........................\.........\xst.prj
.....\.....\........................\.........\xst.scr
.....\.....\........................\simulation\addr_gen.vhd
.....\.....\........................\..........\bmg_stim_gen.vhd
.....\.....\........................\..........\bmg_tb_pkg.vhd
.....\.....\........................\..........\checker.vhd
.....\.....\........................\..........\data_gen.vhd
.....\.....\........................\..........\functional\simcmds.tcl
.....\.....\........................\..........\..........\simulate_isim.bat
.....\.....\........................\..........\..........\simulate_mti.bat
.....\.....\........................\..........\..........\simulate_mti.do
.....\.....\........................\..........\..........\simulate_mti.sh
.....\.....\........................\..........\..........\simulate_ncsim.sh
.....\.....\........................\..........\..........\simulate_vcs.sh
.....\.....\........................\..........\..........\ucli_commands.key
.....\.....\........................\..........\..........\vcs_session.tcl
.....\.....\........................\..........\..........\wave_mti.do
.....\.....\........................\..........\..........\wave_ncsim.sv
.....\.....\........................\..........\MyFIFO_Block_Memory_v7_1_synth.vhd
.....\.....\........................\..........\MyFIFO_Block_Memory_v7_1_tb.vhd
.....\.....\........................\..........\random.vhd
.....\.....\........................\..........\timing\simcmds.tcl
.....\.....\........................\..........\......\simulate_isim.bat
.....\.....\........................\..........\......\simulate_mti.bat
.....\.....\........................\..........\......\simulate_mti.do
.....\.....\........................\..........\......\simulate_mti.sh
.....\.....\........................\..........\......\simulate_ncsim.sh
.....\.....\........................\..........\......\simulate_vcs.sh
.....\.....\........................\..........\......\ucli_commands.key
.....\.....\........................\..........\......\vcs_session.tcl
.....\.....\........................\..........\......\wave_mti.do
.....\.....\........................\..........\......\wave_ncsim.sv
.....\.....\MyFIFO_Block_Memory_v7_1.asy
.....\.....\MyFIFO_Block_Memory_v7_1.gise
.....\.....\MyFIFO_Block_Memory_v7_1.ngc
.....\.....\MyFIFO_Block_Memory_v7_1.v
.....\.....\MyFIFO_Block_Memory_v7_1.veo
.....\.....\MyFIFO_Block_Memory_v7_1.xco
.....\.....\MyFIFO_Block_Memory_v7_1.xise
.....\.....\MyFIFO_Block_Memory_v7_1_flist.txt
.....\.....\MyFIFO_Block_Memory_v7_1_xmdf.tcl
.....\.....\summary.log
.....\.....\tmp\MyFIFO_Block_Memory_v7_1.lso
.....\.....\...\_xmsgs\pn_parser.xmsgs
.....\.....\...\......\xst.xmsgs
.....\MyFIFO.v
.....\prj_5.hdp
.....\....._lib\hdl\bbfifo_16x8.v
.....\.........\...\ClockManager.v
.....\.........\...\ClockManager.v.bak
.....\.........\...\controller_fsm.v
.....\.........\...\DataCapture.v
.....\.........\..
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