Using Verilog HDL language implementation of BCD addition

BCD
...\BCD.cr.mti
...\BCD.mpf
...\BCD.v
...\BCD.v.bak
...\BCD.xml
...\BCD_tb.v
...\BCD_tb.v.bak
...\transcript
...\vsim.wlf
...\work
...\....\@_opt
...\....\.....\_deps
...\....\.....\vopt1gy8kd
...\....\.....\vopt20xh8v
...\....\.....\vopt3gvtw8
...\....\.....\vopt40t3hn
...\....\.....\vopt5grc54
...\....\.....\vopt60qmsh
...\....\.....\vopt7gmydz
...\....\.....\vopt80k72d
...\....\.....\vopt9gignt
...\....\.....\vopta0hsa8
...\....\.....\voptbgf2zm
...\....\@b@c@d
...\....\......\_primary.dat
...\....\......\_primary.dbs
...\....\......\_primary.vhd
...\....\......\verilog.asm
...\....\......\verilog.rw
...\....\@b@c@d_tb
...\....\.........\_primary.dat
...\....\.........\_primary.dbs
...\....\.........\_primary.vhd
...\....\.........\verilog.asm
...\....\.........\verilog.rw
...\....\_info
...\....\_temp
...\....\.....\vlog058m6c
...\....\.....\vlogk9i12n
...\....\.....\vlogq2nxg9
...\....\_vmake

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