Traffic light controlled crossroads of traffic lights analog state machine implementation, no time

Traffic_led\db\prev_cmp_Traffic_led.asm.qmsg
...........\..\prev_cmp_Traffic_led.eda.qmsg
...........\..\prev_cmp_Traffic_led.fit.qmsg
...........\..\prev_cmp_Traffic_led.map.qmsg
...........\..\prev_cmp_Traffic_led.qmsg
...........\..\prev_cmp_Traffic_led.sim.qmsg
...........\..\prev_cmp_Traffic_led.tan.qmsg
...........\..\Traffic_led.asm.qmsg
...........\..\Traffic_led.asm_labs.ddb
...........\..\Traffic_led.cbx.xml
...........\..\Traffic_led.cmp.bpm
...........\..\Traffic_led.cmp.cdb
...........\..\Traffic_led.cmp.ecobp
...........\..\Traffic_led.cmp.hdb
...........\..\Traffic_led.cmp.kpt
...........\..\Traffic_led.cmp.logdb
...........\..\Traffic_led.cmp.rdb
...........\..\Traffic_led.cmp.tdb
...........\..\Traffic_led.cmp0.ddb
...........\..\Traffic_led.cmp_merge.kpt
...........\..\Traffic_led.db_info
...........\..\Traffic_led.eco.cdb
...........\..\Traffic_led.eda.qmsg
...........\..\Traffic_led.eds_overflow
...........\..\Traffic_led.fit.qmsg
...........\..\Traffic_led.fnsim.hdb
...........\..\Traffic_led.fnsim.qmsg
...........\..\Traffic_led.hier_info
...........\..\Traffic_led.hif
...........\..\Traffic_led.lpc.html
...........\..\Traffic_led.lpc.rdb
...........\..\Traffic_led.lpc.txt
...........\..\Traffic_led.map.bpm
...........\..\Traffic_led.map.cdb
...........\..\Traffic_led.map.ecobp
...........\..\Traffic_led.map.hdb
...........\..\Traffic_led.map.kpt
...........\..\Traffic_led.map.logdb
...........\..\Traffic_led.map.qmsg
...........\..\Traffic_led.map_bb.cdb
...........\..\Traffic_led.map_bb.hdb
...........\..\Traffic_led.map_bb.logdb
...........\..\Traffic_led.pre_map.cdb
...........\..\Traffic_led.pre_map.hdb
...........\..\Traffic_led.rtlv.hdb
...........\..\Traffic_led.rtlv_sg.cdb
...........\..\Traffic_led.rtlv_sg_swap.cdb
...........\..\Traffic_led.sgdiff.cdb
...........\..\Traffic_led.sgdiff.hdb
...........\..\Traffic_led.sim.cvwf
...........\..\Traffic_led.sim.qmsg
...........\..\Traffic_led.sim.rdb
...........\..\Traffic_led.simfam
...........\..\Traffic_led.sld_design_entry.sci
...........\..\Traffic_led.sld_design_entry_dsc.sci
...........\..\Traffic_led.smp_dump.txt
...........\..\Traffic_led.syn_hier_info
...........\..\Traffic_led.tan.qmsg
...........\..\Traffic_led.tis_db_list.ddb
...........\..\Traffic_led.tmw_info
...........\..\Traffic_led_global_asgn_op.abo
...........\..\wed.wsf
...........\incremental_db\compiled_partitions\Traffic_led.root_partition.cmp.atm
...........\..............\...................\Traffic_led.root_partition.cmp.dfp
...........\..............\...................\Traffic_led.root_partition.cmp.hdbx
...........\..............\...................\Traffic_led.root_partition.cmp.kpt
...........\..............\...................\Traffic_led.root_partition.cmp.logdb
...........\..............\...................\Traffic_led.root_partition.cmp.rcf
...........\..............\...................\Traffic_led.root_partition.map.atm
...........\..............\...................\Traffic_led.root_partition.map.dpi
...........\..............\...................\Traffic_led.root_partition.map.hdbx
...........\..............\...................\Traffic_led.root_partition.map.kpt
...........\..............\README
...........\simulation\modelsim\gate_work\@traffic_led\_primary.dat
...........\..........\........\.........\............\_primary.vhd
...........\..........\........\.........\............_vlg_tst\_primary.dat
...........\..........\........\.........\....................\_primary.vhd
...........\..........\........\.........\_info
...........\..........\........\.........\.opt\._verilog_libs_stratixii_ver_stratixii_and1_fast.asm
...........\..........\........\.........\....\._verilog_libs_stratixii_ver_stratixii_and1_fast.dt2
...........\..........\........\.........\....\._verilog_libs_stratixii_ver_stratixii_asynch_io_fast.asm
...........\..........\........\.........\....\._verilog_libs_stratixii_ver_stratixii_asynch_io_fast.dt2
...........\..........\........\.........\....\._verilog_libs_stratixii_ver_stratixii_asynch_io_fast__1.asm
...........\.........

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