Sap-1 implementation in FPGA

SAP
...\Accumulator.v
...\Accumulator.v.bak
...\addsub.v
...\addsub.v.bak
...\Clk.v
...\Clk.v.bak
...\controller sequencer.v
...\controller sequencer.v.bak
...\CU.v
...\CU.v.bak
...\input_mar.v
...\input_mar.v.bak
...\ir.v
...\ir.v.bak
...\main.v
...\main.v.bak
...\outdis.v
...\outdis.v.bak
...\outDisplay.v.bak
...\pc.cr.mti
...\pc.mpf
...\pc.v
...\pc.v.bak
...\Ram16k.v
...\Ram16k.v.bak
...\RegisterB.v
...\RegisterB.v.bak
...\Ring_counter.v
...\Ring_counter.v.bak
...\vsim.wlf
...\work
...\....\_info
...\....\_lib.qdb
...\....\_lib1_0.qdb
...\....\_lib1_0.qpg
...\....\_lib1_1.qdb
...\....\_lib1_1.qpg
...\....\_lib1_3.qdb
...\....\_lib1_3.qpg
...\....\_lib1_4.qdb
...\....\_lib1_4.qpg
...\....\_lib1_5.qdb
...\....\_lib1_5.qpg
...\....\_lib1_6.qdb
...\....\_lib1_6.qpg
...\....\_lib1_7.qdb
...\....\_lib1_7.qpg
...\....\_lib1_8.qdb
...\....\_lib1_8.qpg
...\....\_vmake

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