module t1 (clk,quot) input clk output quot reg quot reg[23:0] tc always@(posedge clk) begin tc<=tc+1 b1 if (tc==24 h013fff) begin quot<=1 tc<=0 end else quot<=0 end endmodule

miankao\1.v
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.......\..\duoweishumaguan.eco.cdb
.......\..\duoweishumaguan.sld_design_entry.sci
.......\..\duoweishumaguan_global_asgn_op.abo
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.......\..\prev_cmp_duoweishumaguan.fit.qmsg
.......\..\prev_cmp_duoweishumaguan.map.qmsg
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.......\..\prev_cmp_duoweishumaguan.tan.qmsg
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.......\..............\...................\duoweishumaguan.root_partition.cmp.hdbx
.......\..............\...................\duoweishumaguan.root_partition.cmp.kpt
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.......\..............\...................\duoweishumaguan.root_partition.map.dpi
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.......\..............\README
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.......\db
.......\incremental_db
miankao

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