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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-05-06
  • Size : 1.09mb
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  • Author :xieba*****
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Binary code conversion design, complete design engineering files in data_convert file folder
Packet file list
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counter\_ngo
.......\....\netlist.lst
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.......\......\fuse.xmsgs
.......\......\map.xmsgs
.......\......\netgen.xmsgs
.......\......\ngdbuild.xmsgs
.......\......\par.xmsgs
.......\......\trce.xmsgs
.......\......\vhpcomp.xmsgs
.......\......\xst.xmsgs
.......\counter.ise
.......\counter.ise_ISE_Backup
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.......\fourbitcounter_pad.txt
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.......\fourbitcounter_vhdl.prj
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.......\isim.hdlsourcefiles
.......\isim.log
.......\isim.tmp_save
.......\.............\_1
.......\isim
.......\....\file graph
.......\....\simprim.auxlib
.......\....\..............\hdllib.ref
.......\....\..............\vcomponents
.......\....\..............\...........\mingw
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.......\....\..............\...........\vcomponents.h
.......\....\..............\vpackage
.......\....\..............\........\mingw
.......\....\..............\........\.....\vpackage.obj
.......\....\..............\........\vpackage.h
.......\....\..............\x_buf
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.......\....\..............\.....\x_buf_v.h
.......\....\..............\x_bufgmux
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.......\....\..............\.........\.....\x_bufgmux_v.obj
.......\....\..............\.........\x_bufgmux_v.h
.......\....\..............\x_ff
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.......\....\..............\....\.....\x_ff_v.obj
.......\....\..............\....\x_ff_v.h
.......\....\..............\x_inv
.......\....\..............\.....\mingw
.......\....\..............\.....\.....\x_inv_v.obj
.......\....\..............\.....\x_inv_v.h
.......\....\..............\x_lut4
.......\....\..............\......\mingw
.......\....\..............\......\.....\x_lut4_v.obj
.......\....\..............\......\x_lut4_v.h
.......\....\..............\x_mux2
.......\....\..............\......\mingw
.......\....\..............\......\.....\x_mux2_v.obj
.......\....\..............\......\x_mux2_v.h
.......\....\..............\x_obuf
.......\....\..............\......\mingw
.......\....\..............\......\.....\x_obuf_v.obj
.......\....\..............\......\x_obuf_v.h
.......\....\..............\x_one
.......\....\..............\.....\mingw
.......\....\..............\.....\.....\x_one_v.obj
.......\....\..............\.....\x_one_v.h
.......\....\..............\x_roc
.......\....\..............\.....\mingw
.......\....\..............\.....\.....\x_roc_v.obj
.......\....\..............\.....\x_roc_v.h
.......\....\..............\x_toc
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