The ModelSim Simulation, a large number of VHDL procedures, validation, great value!

example_c\addr_decoder.v
.........\add_4.v
.........\CNT_LFSR_DIV13.v
.........\CNT_LFSR_DIV13_1.v
.........\CNT_LFSR_DIV13_t.v
.........\CNT_LFSR_DIV13_test.v
.........\compare_8b.v
.........\encode8_3.v
.........\encode8_3_pri.v
.........\example.v
.........\example_1.v
.........\example_2.txt
.........\FSM_1.v
.........\fsm_2.txt
.........\fsm_3.v
.........\fsm_3_modify.v
.........\fsm_test.v
.........\LFSR_8bit.v
.........\LFSR_8bit_test.v
.........\LFSR_GENERiC_MOD.v
.........\modelsim.ini
.........\mult_if_1.v
.........\mult_if_2.v
.........\mux4_1.v
.........\one_bit_adder.v
.........\sel.mpf
.........\sell_out.v
.........\sell_out_1.v
.........\sell_out_test.v
.........\sel_add.v
.........\sel_add1.v
.........\sel_add2.v
.........\serial_detected.v
.........\serial_detected.v.bak
.........\serial_detected_test.v
.........\tcl_stacktrace.txt
.........\testbench.v
.........\transcript
.........\work\_info
.........\新建 文本文档.txt
.........\work
example_c

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