opensource Verilog bitcon miner from gitb

Open-Source-FPGA-Bitcoin-Miner-master
.....................................\.gitignore
.....................................\LICENSE.txt
.....................................\README.md
.....................................\boards
.....................................\......\DE2_115
.....................................\......\.......\DE2_115.qsf
.....................................\......\.......\DE2_115.sdc
.....................................\......\README.md
.....................................\cores
.....................................\.....\README.md
.....................................\.....\crc
.....................................\.....\...\crc32.v
.....................................\.....\...\crc32_tb.v
.....................................\.....\...\simulate.sh
.....................................\.....\cyclone_iv_pll
.....................................\.....\..............\hashing_pll.v
.....................................\.....\unoptimized
.....................................\.....\...........\README.md
.....................................\.....\...........\sha-256-functions.v
.....................................\.....\...........\sha256_transform.v
.....................................\.....\unoptimized_virtual_wire_top.v
.....................................\.....\virtual_wire
.....................................\.....\............\virtual_wire.v
.....................................\projects
.....................................\........\3C120_uart_comm_Test
.....................................\........\....................\3C120_uart_comm_Test.qpf
.....................................\........\....................\3C120_uart_comm_Test.qsf
.....................................\........\....................\README.md
.....................................\........\....................\constraints
.....................................\........\....................\...........\3C120.sdc
.....................................\........\....................\hdl
.....................................\........\....................\...\3C120_uart_comm_Test.v
.....................................\........\....................\...\main_pll.v
.....................................\........\....................\stp1.stp
.....................................\........\....................\working
.....................................\........\....................\.......\.gitignore
.....................................\........\BeMicro
.....................................\........\.......\README.md
.....................................\........\.......\fpgaminer.qpf
.....................................\........\.......\fpgaminer.qsf
.....................................\........\.......\fpgaminer.sdc
.....................................\........\.......\src
.....................................\........\.......\...\fpgaminer_top.v
.....................................\........\DE2_115_NIOS_Ethernet_Test
.....................................\........\..........................\.gitignore
.....................................\........\..........................\README.md
.....................................\........\..........................\software
.....................................\........\..........................\........\fpgaminer_controller
.....................................\........\..........................\........\....................\main.c
.....................................\........\..........................\........\....................\socket.c
.....................................\........\..........................\........\....................\socket.h
.....................................\........\..........................\........\....................\stdint.h
.....................................\........\..........................\........\....................\w5100.c
.....................................\........\..........................\........\....................\w5100.h
.....................................\........\..........................\src
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