Motor stepper motor controller using the altera MAX II CPLD to do.

madadianji_controller\an488_design_example\code\stepmot.v
.....................\....................\modelsim\stepmot.v
.....................\....................\........\stepmot_sim.cr.mti
.....................\....................\........\stepmot_sim.mpf
.....................\....................\........\test_stepmot.v
.....................\....................\........\transcript
.....................\....................\........\wave.bmp
.....................\....................\........\wave.do
.....................\....................\........\.ork\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\verilog.psm
.....................\....................\........\....\............................\_primary.dat
.....................\....................\........\....\............................\_primary.vhd
.....................\....................\........\....\divider\verilog.psm
.....................\....................\........\....\.......\_primary.dat
.....................\....................\........\....\.......\_primary.vhd
.....................\....................\........\....\.......1\verilog.psm
.....................\....................\........\....\........\_primary.dat
.....................\....................\........\....\........\_primary.vhd
.....................\....................\........\....\maxii_and1\verilog.psm
.....................\....................\........\....\..........\_primary.dat
.....................\....................\........\....\..........\_primary.vhd
.....................\....................\........\....\..........6\verilog.psm
.....................\....................\........\....\...........\_primary.dat
.....................\....................\........\....\...........\_primary.vhd
.....................\....................\........\....\.......synch_lcell\verilog.psm
.....................\....................\........\....\..................\_primary.dat
.....................\....................\........\....\..................\_primary.vhd
.....................\....................\........\....\......b17mux21\verilog.psm
.....................\....................\........\....\..............\_primary.dat
.....................\....................\........\....\..............\_primary.vhd
.....................\....................\........\....\.......5mux21\verilog.psm
.....................\....................\........\....\.............\_primary.dat
.....................\....................\........\....\.............\_primary.vhd
.....................\....................\........\....\.......mux21\verilog.psm
.....................\....................\........\....\............\_primary.dat
.....................\....................\........\....\............\_primary.vhd
.....................\....................\........\....\......crcblock\verilog.psm
.....................\....................\........\....\..............\_primary.dat
.....................\....................\........\....\..............\_primary.vhd
.....................\....................\........\....\......dffe\verilog.psm
.....................\....................\........\....\..........\_primary.dat
.....................\....................\........\....\..........\_primary.vhd
.....................\....................\........\....\......io\verilog.psm
.....................\....................\........\....\........\_primary.dat
.....................\....................\........\....\........\_primary.vhd
.....................\....................\........\....\......jtag\verilog.psm
.....................\....................\........\....\..........\_primary.dat
.....................\....................\........\....\..........\_primary.vhd
.....................\....................\........\....\......latch\verilog.psm
.....................\....................\........\....\...........\_primary.dat
.....................\....................\........\....\...........\_primary.vhd
.....................\....................\........\....\.......cell\verilog.psm
...........

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．