Based on Verilog HDL language, written in frequency meter.

S2
..\count10.bsf
..\count10.v
..\db
..\..\plj.asm.qmsg
..\..\plj.asm_labs.ddb
..\..\plj.cbx.xml
..\..\plj.cmp.cdb
..\..\plj.cmp.hdb
..\..\plj.cmp.kpt
..\..\plj.cmp.logdb
..\..\plj.cmp.rdb
..\..\plj.cmp.tdb
..\..\plj.cmp0.ddb
..\..\plj.dbp
..\..\plj.db_info
..\..\plj.eco.cdb
..\..\plj.eds_overflow
..\..\plj.fit.qmsg
..\..\plj.hier_info
..\..\plj.hif
..\..\plj.map.cdb
..\..\plj.map.hdb
..\..\plj.map.logdb
..\..\plj.map.qmsg
..\..\plj.pre_map.cdb
..\..\plj.pre_map.hdb
..\..\plj.psp
..\..\plj.rpp.qmsg
..\..\plj.rtlv.hdb
..\..\plj.rtlv_sg.cdb
..\..\plj.rtlv_sg_swap.cdb
..\..\plj.sgate.rvd
..\..\plj.sgate_sm.rvd
..\..\plj.sgdiff.cdb
..\..\plj.sgdiff.hdb
..\..\plj.signalprobe.cdb
..\..\plj.sim.hdb
..\..\plj.sim.qmsg
..\..\plj.sim.rdb
..\..\plj.sim.vwf
..\..\plj.sld_design_entry.sci
..\..\plj.sld_design_entry_dsc.sci
..\..\plj.syn_hier_info
..\..\plj.tan.qmsg
..\..\wed.zsf
..\display.bsf
..\display.v
..\fp.bsf
..\fp.v
..\fre_ctrl.bsf
..\fre_ctrl.v
..\jsq.bdf
..\latch_16.bsf
..\latch_16.v
..\plj.asm.rpt
..\plj.cdf
..\plj.done
..\plj.dpf
..\plj.fit.rpt
..\plj.fit.smsg
..\plj.fit.summary
..\plj.flow.rpt
..\plj.map.rpt
..\plj.map.summary
..\plj.pin
..\plj.pof
..\plj.qpf
..\plj.qsf
..\plj.qws
..\plj.sim.rpt
..\plj.tan.rpt
..\plj.tan.summary
..\plj.vwf

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