ISE platform simulation UART and transceiver.

UART0407\.lso
........\coregen_xil_668_46.cgc
........\coregen_xil_668_46.cgp
........\ctrl.cmd_log
........\ctrl.spl
........\ctrl.sym
........\data_to_uart.cmd_log
........\data_to_uart.prj
........\data_to_uart.spl
........\data_to_uart.stx
........\data_to_uart.sym
........\data_to_uart.xst
........\data_to_uart_vhdl.prj
........\fenpincnter.cmd_log
........\fenpincnter.prj
........\fenpincnter.spl
........\fenpincnter.stx
........\fenpincnter.sym
........\fenpincnter.vhd
........\fenpincnter.xst
........\fenpincnter_vhdl.prj
........\ipcore_dir\coregen.cgc
........\..........\coregen.cgp
........\..........\coregen.log
........\..........\coregen.rsp
........\..........\fifo_generator_readme.txt
........\..........\fifo_generator_ug175.pdf
........\..........\uart_rx_fifo.asy
........\..........\uart_rx_fifo.gise
........\..........\uart_rx_fifo.ncf
........\..........\uart_rx_fifo.ngc
........\..........\uart_rx_fifo.sym
........\..........\uart_rx_fifo.v
........\..........\uart_rx_fifo.veo
........\..........\uart_rx_fifo.vhd
........\..........\uart_rx_fifo.vho
........\..........\uart_rx_fifo.xco
........\..........\uart_rx_fifo.xco.bak
........\..........\uart_rx_fifo.xise
........\..........\uart_rx_fifo_flist.txt
........\..........\uart_rx_fifo_xmdf.tcl
........\..........\uart_tx_fifo.asy
........\..........\uart_tx_fifo.gise
........\..........\uart_tx_fifo.ncf
........\..........\uart_tx_fifo.ngc
........\..........\uart_tx_fifo.sym
........\..........\uart_tx_fifo.v
........\..........\uart_tx_fifo.veo
........\..........\uart_tx_fifo.vhd
........\..........\uart_tx_fifo.vho
........\..........\uart_tx_fifo.xco
........\..........\uart_tx_fifo.xco.bak
........\..........\uart_tx_fifo.xise
........\..........\uart_tx_fifo_flist.txt
........\..........\uart_tx_fifo_xmdf.tcl
........\..........\_xmsgs\ngcbuild.xmsgs
........\..........\......\pn_parser.xmsgs
........\..........\......\xst.xmsgs
........\.seconfig\uart.xreport
........\.........\UART0407.projectmgr
........\.........\UART1.xreport
........\pa.fromNetlist.tcl
........\pepExtractor.prj
........\planAhead.ngc2edif.log
........\........._run_1\planAhead.jou
........\...............\planAhead.log
........\...............\planAhead_run.log
........\..............2\UART0407.data\constrs_1\designprops.xml
........\...............\.............\.........\fileset.xml
........\...............\.............\.........\usercols.xml
........\...............\.............\runs\impl_1.psg
........\...............\.............\....\runs.xml
........\...............\.............\sources_1\chipscope.xml
........\...............\.............\.........\fileset.xml
........\...............\.............\.........\ports.xml
........\...............\.............\wt\webtalk_pa.xml
........\...............\UART0407.ppr
........\rx_tx_en.cmd_log
........\rx_tx_en.prj
........\rx_tx_en.spl
........\rx_tx_en.stx
........\rx_tx_en.sym
........\rx_tx_en.vhd
........\rx_tx_en.xst
........\rx_tx_en_vhdl.prj
........\sch2HdlBatchFile
........\tx_control.cmd_log
........\tx_control.prj
........\tx_control.spl
........\tx_control.stx
........\tx_control.sym
........\tx_control.v
........\tx_control.vhd
........\tx_control.xst
........\tx_control_vhdl.prj
........\tx_rx_en.bmm
........\uart.cmd_log
........\UART.jhd
........\uart.lso
........\uart.ngc

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