single cycle CPU element design with Verilog

SC_CPU
......\db
......\..\altsyncram_0t91.tdf
......\..\altsyncram_15a1.tdf
......\..\altsyncram_v4a1.tdf
......\..\logic_util_heursitic.dat
......\..\prev_cmp_SC_CPU.qmsg
......\..\SC_CPU.ae.hdb
......\..\SC_CPU.amm.cdb
......\..\SC_CPU.asm.qmsg
......\..\SC_CPU.asm.rdb
......\..\SC_CPU.asm_labs.ddb
......\..\SC_CPU.cbx.xml
......\..\SC_CPU.cmp.bpm
......\..\SC_CPU.cmp.cdb
......\..\SC_CPU.cmp.hdb
......\..\SC_CPU.cmp.kpt
......\..\SC_CPU.cmp.logdb
......\..\SC_CPU.cmp.rdb
......\..\SC_CPU.cmp0.ddb
......\..\SC_CPU.cmp1.ddb
......\..\SC_CPU.cmp_merge.kpt
......\..\SC_CPU.db_info
......\..\SC_CPU.eda.qmsg
......\..\SC_CPU.fit.qmsg
......\..\SC_CPU.hc_netlist.qmsg
......\..\SC_CPU.hc_ready.qmsg
......\..\SC_CPU.hier_info
......\..\SC_CPU.hif
......\..\SC_CPU.idb.cdb
......\..\SC_CPU.lpc.html
......\..\SC_CPU.lpc.rdb
......\..\SC_CPU.lpc.txt
......\..\SC_CPU.map.bpm
......\..\SC_CPU.map.cdb
......\..\SC_CPU.map.hdb
......\..\SC_CPU.map.kpt
......\..\SC_CPU.map.logdb
......\..\SC_CPU.map.qmsg
......\..\SC_CPU.map_bb.cdb
......\..\SC_CPU.map_bb.hdb
......\..\SC_CPU.map_bb.logdb
......\..\SC_CPU.pre_map.cdb
......\..\SC_CPU.pre_map.hdb
......\..\SC_CPU.ram0_scdatamem_e6c400a0.hdl.mif
......\..\SC_CPU.rpp.qmsg
......\..\SC_CPU.rtlv.hdb
......\..\SC_CPU.rtlv_sg.cdb
......\..\SC_CPU.rtlv_sg_swap.cdb
......\..\SC_CPU.sgate.rvd
......\..\SC_CPU.sgate_sm.rvd
......\..\SC_CPU.sgdiff.cdb
......\..\SC_CPU.sgdiff.hdb
......\..\SC_CPU.sld_design_entry.sci
......\..\SC_CPU.sld_design_entry_dsc.sci
......\..\SC_CPU.smart_action.txt
......\..\SC_CPU.sta.qmsg
......\..\SC_CPU.sta.rdb
......\..\SC_CPU.sta_cmp.3_slow.tdb
......\..\SC_CPU.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
......\..\SC_CPU.stingray_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
......\..\SC_CPU.stingray_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
......\..\SC_CPU.syn_hier_info
......\..\SC_CPU.tis_db_list.ddb
......\..\SC_CPU.tmw_info
......\dff32.v
......\hc_output
......\.........\SC_CPU.constraints.sdc
......\.........\SC_CPU.hc_output_files
......\.........\SC_CPU.l2p_netlist.map
......\.........\SC_CPU.names_drv_tbl
......\.........\SC_CPU.qpef
......\.........\SC_CPU.qref
......\.........\SC_CPU.sta_col
......\.........\SC_CPU.tcl
......\.........\SC_CPU.v
......\incremental_db
......\..............\compiled_partitions
......\..............\...................\SC_CPU.db_info
......\..............\...................\SC_CPU.root_partition.cmp.cbp
......\..............\...................\SC_CPU.root_partition.cmp.cdb
......\..............\...................\SC_CPU.root_partition.cmp.dfp
......\..............\...................\SC_CPU.root_partition.cmp.hdb
......\..............\...................\SC_CPU.root_partition.cmp.kpt
......\..............\...................\SC_CPU.root_partition.cmp.logdb
......\..............\...................\SC_CPU.root_partition.cmp.rcfdb
......\..............\...................\SC_CPU.root_partition.cmp.rcfdb.cdb
......\..............\...................\SC_CPU.root_partition.cmp.re.rcfdb
......\..............\...................\SC_CPU.root_partition.cmp.re.rcfdb.cdb
......\..............\...................\SC_CPU.root_partition.map.cbp
......\..............\...................\SC_CPU.root_partition.map.cdb
......\..............\...................\SC_CPU.root_partition.map.dpi
......\..............\...................\SC_CPU.root_partition.map.hdb
......\..............\...................\SC_CPU.root_partition.map.kpt
......\..............\README
......\mux2x32.v
......\mux2x5.v
......\sccomp_dataflow.v
......\sccpu_dataflow.v
......\sccu_dataflow.v

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