Verilog implementation of the AES algorithm, easy-to-understand

aes_core
........\bench
........\.....\CVS
........\.....\...\Entries
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........\.....\...\Root
........\.....\verilog
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........\.....\.......\test_bench_top.v
........\CVS
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........\doc
........\...\aes.pdf
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........\rtl
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........\...\verilog
........\...\.......\AES
........\...\.......\AES.zip
........\...\.......\aes_cipher_top.v
........\...\.......\aes_inv_cipher_top.v
........\...\.......\aes_inv_sbox.v
........\...\.......\aes_key_expand_128.v
........\...\.......\aes_rcon.v
........\...\.......\aes_sbox.v
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........\...\.......\timescale.v
........\sim
........\...\CVS
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........\...\rtl_sim
........\...\.......\bin
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........\...\.......\...\Makefile
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........\...\.......\run
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........\...\.......\...\waves
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........\...\.......\...\.....\waves.do
........\syn
........\...\bin
........\...\...\comp.dc
........\...\...\CVS
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........\...\...\design_spec.dc
........\...\...\lib_spec.dc
........\...\...\read.dc
........\...\CVS
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........\vim_session.vim

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