FPGA control the vga display the source code written in VERILOG

abc
...\generic_dpram.v
...\generic_spram.v
...\test
...\....\sync_check.v
...\....\test_bench_top.v
...\....\test_bench_top.v.bak
...\....\wb_b3_check.v
...\....\wb_mast_model.v
...\....\wb_model_defines.v
...\....\wb_slv_model.v
...\timescale.v
...\vga_clkgen.v
...\vga_colproc.v
...\vga_core_enh.doc
...\vga_csm_pb.v
...\vga_curproc.v
...\vga_cur_cregs.v
...\vga_defines.v
...\vga_enh_top.v
...\vga_fifo.v
...\vga_fifo_dc.v
...\vga_pgen.v
...\vga_tgen.v
...\vga_vtim.v
...\vga_wb_master.v
...\vga_wb_slave.v

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