Serial AD/DA experiments. Verilog beginners experimental procedures. Been in quartus under test success.

serial_adda\.lso
...........\AD.v
...........\AD_SERIES.v
...........\DA_SERISE.v
...........\device_usage_statistics.html
...........\isim\unisim_ver.auxlib\dcm__clock__divide__by__2\dcm__clock__divide__by__2.h
...........\....\.................\.........................\mingw\dcm__clock__divide__by__2.obj
...........\....\.................\............lost\dcm__clock__lost.h
...........\....\.................\................\mingw\dcm__clock__lost.obj
...........\....\.................\.....maximum__period__check\dcm__maximum__period__check.h
...........\....\.................\...........................\mingw\dcm__maximum__period__check.obj
...........\....\.................\hdllib.ref
...........\....\.................\_b_u_f_g\mingw\_b_u_f_g.obj
...........\....\.................\........\_b_u_f_g.h
...........\....\.................\.d_c_m\mingw\_d_c_m.obj
...........\....\.................\......\_d_c_m.h
...........\....\.................\.i_b_u_f_g\mingw\_i_b_u_f_g.obj
...........\....\.................\..........\_i_b_u_f_g.h
...........\....\work\glbl\glbl.h
...........\....\....\....\mingw\glbl.obj
...........\....\....\hdllib.ref
...........\....\....\hdpdeps.ref
...........\....\....\main\main.h
...........\....\....\....\.ingw\main.obj
...........\....\....\....\xsimmain.cpp
...........\....\....\test\mingw\test.obj
...........\....\....\....\test.h
...........\....\....\....\xsimtest.cpp
...........\....\....\v2__dcm\mingw\v2__dcm.obj
...........\....\....\.......\v2__dcm.h
...........\....\....\.lg03\v2__dcm.bin
...........\....\....\....9\_a_d.bin
...........\....\....\...2D\glbl.bin
...........\....\....\.....\main.bin
...........\....\....\...34\test.bin
...........\....\....\_a_d\mingw\_a_d.obj
...........\....\....\....\_a_d.h
...........\isim.cmd
...........\isim.hdlsourcefiles
...........\isim.log
...........\.....tmp_save\_1
...........\isimwavedata.xwv
...........\main.bgn
...........\main.bit
...........\main.bld
...........\main.cel
...........\main.cmd_log
...........\main.drc
...........\main.lso
...........\main.ncd
...........\main.ngc
...........\main.ngd
...........\main.ngr
...........\main.pad
...........\main.par
...........\main.pcf
...........\main.prj
...........\main.stx
...........\main.syr
...........\main.twr
...........\main.twx
...........\main.ucf
...........\main.ucf.bak
...........\main.unroutes
...........\main.ut
...........\main.v
...........\main.xpi
...........\main.xst
...........\main_beh.prj
...........\main_isim_beh.exe
...........\main_last_par.ncd
...........\main_map.mrp
...........\main_map.ncd
...........\main_map.ngm
...........\main_pad.csv
...........\main_pad.txt
...........\main_prev_built.ngd
...........\main_summary.html
...........\main_usage.xml
...........\main_vhdl.prj
...........\parall_ad_da.ntrc_log
...........\results.txt
...........\serial_adda.ise
...........\serial_adda.ise_ISE_Backup
...........\serial_adda.ntrc_log
...........\test.ant
...........\test.jhd
...........\test.tbw
...........\test.tfw
...........\test.xwv
...........\test.xwv_bak
...........\test_beh.prj
...........\test_bencher.prj
...........\test_isim_beh.exe
...........\v4_dcm.v
...........\v4_dcm.xaw
...........\v4_dcm_arwz.ucf
...........\xaw2verilog.log
...........\xilinxsim.ini
...........\.st\dump.xst\main.prj\ntrc.scr

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