Verilog beginners experimental procedures. Been in quartus under test success.

key\CLK_DIV.v
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...\.st\dump.xst\main.prj\ntrc.scr
...\...\work\hdllib.ref
...\...\....\vlg03\v2__dcm.bin
...\...\....\...1D\_d_e_b_o_u_n_c_e.bin
...\...\....\.....\_k_e_y___s_c_a_n.bin
...\...\....\...2D\main.bin
...\...\....\...41\_t_r_a_n___h_e_x___l_e_d.bin
...\...\....\...65\v4__dcm.bin
...\...\....\...7C\_c_l_k___d_i_v.bin
...\_impact.cmd
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...\.ngo\netlist.lst
...\.xmsgs\bitgen.xmsgs
...\......\map.xmsgs
...\......\ngdbuild.xmsgs
...\......\par.xmsgs
...\......\trce.xmsgs
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...\xst\dump.xst\main.prj\ngx\notopt
...\...\........\........\...\opt
...\...\........\........\ngx
...\...\........\main.prj
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...\...\....\vlg1D
...\...\....\vlg2D
...\...\....\vlg41
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key

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