Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains

RISC-CPU\.nclaunch.dd
........\.nclaunch.dd.bak
........\.simvision\dbrowser-bookmarks
........\..........\schematic-bookmarks
........\..........\source-bookmarks
........\accum.v
........\addr.v
........\alu_out.ddc
........\alu_out.v
........\cds.lib
........\choose.v
........\clkgen.v
........\command.log
........\counter.v
........\cpu.txt
........\cpu.v
........\datactl.v
........\data_choose.v
........\default.svf
........\filenames.log
........\hdl.var
........\INCA_libs\worklib\.cdsvmod
........\.........\.......\.inca.db.179.lnx86
........\.........\.......\inca.lnx86.179.pak
........\machine.v
........\ncelab.log
........\nclaunch.key
........\ncsim.key
........\ncsim.log
........\ncvlog.log
........\ram.v
........\register.v
........\RSUC.v
........\tb.v
........\typical.db
........\umc18\.cdsvmod
........\.....\.inca.db.179.lnx86
........\.....\inca.lnx86.179.pak
........\umc18.sdb
........\umc18.v
........\waves.shm\waves-1.trn
........\.........\waves-10.trn
........\.........\waves-11.trn
........\.........\waves-12.trn
........\.........\waves-13.trn
........\.........\waves-2.trn
........\.........\waves-3.trn
........\.........\waves-4.trn
........\.........\waves-5.trn
........\.........\waves-6.trn
........\.........\waves-7.trn
........\.........\waves-8.trn
........\.........\waves-9.trn
........\.........\waves.dsn
........\.........\waves.trn
........\INCA_libs\worklib
........\.simvision
........\INCA_libs
........\umc18
........\waves.shm
RISC-CPU

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