ZLG Fusion StartKit, fpga development board test routines, FlashROM experiment

FlashROM实验\Project\Flash_ROM\constraint\Flash_ROM_Top.pdc
............\.......\.........\designer\impl1\designer.log
............\.......\.........\........\.....\designer_genhdl.log
............\.......\.........\........\.....\designer_gen_ba.log
............\.......\.........\........\.....\FlashROM16.tcl
............\.......\.........\........\.....\Flash_ROM_Top.adb
............\.......\.........\........\.....\..............dtf\verify.log
............\.......\.........\........\.....\Flash_ROM_Top.ide_des
............\.......\.........\........\.....\Flash_ROM_Top.pdb
............\.......\.........\........\.....\Flash_ROM_Top.pdb.depends
............\.......\.........\........\.....\Flash_ROM_Top.tcl
............\.......\.........\........\.....\Flash_ROM_Top_ba.sdf
............\.......\.........\........\.....\Flash_ROM_Top_ba.v
............\.......\.........\........\.....\simulation\postlayout\@flash_@r@o@m_@top\verilog.psm
............\.......\.........\........\.....\..........\..........\..................\_primary.dat
............\.......\.........\........\.....\..........\..........\..................\_primary.vhd
............\.......\.........\........\.....\..........\..........\stimulus\verilog.psm
............\.......\.........\........\.....\..........\..........\........\_primary.dat
............\.......\.........\........\.....\..........\..........\........\_primary.vhd
............\.......\.........\........\.....\..........\..........\tb_clock_minmax\verilog.psm
............\.......\.........\........\.....\..........\..........\...............\_primary.dat
............\.......\.........\........\.....\..........\..........\...............\_primary.vhd
............\.......\.........\........\.....\..........\..........\.estbench\verilog.psm
............\.......\.........\........\.....\..........\..........\.........\_primary.dat
............\.......\.........\........\.....\..........\..........\.........\_primary.vhd
............\.......\.........\........\.....\..........\..........\_info
............\.......\.........\Flash_ROM.prj
............\.......\.........\hdl\FlashROM_Out.v
............\.......\.........\...\Flash_ROM_Ctr.v
............\.......\.........\...\Flash_ROM_Top.v
............\.......\.........\...\hdlsynchk.tcl
............\.......\.........\simulation\FlashROM16.mem
............\.......\.........\..........\meminit.dat
............\.......\.........\..........\modelsim.ini
............\.......\.........\..........\modelsim.ini.sav
............\.......\.........\..........\modelsim.log
............\.......\.........\..........\presynth\@flash@r@o@m16\verilog.psm
............\.......\.........\..........\........\..............\_primary.dat
............\.......\.........\..........\........\..............\_primary.vhd
............\.......\.........\..........\........\............_@out\verilog.psm
............\.......\.........\..........\........\.................\_primary.dat
............\.......\.........\..........\........\.................\_primary.vhd
............\.......\.........\..........\........\......_@r@o@m_@ctr\verilog.psm
............\.......\.........\..........\........\..................\_primary.dat
............\.......\.........\..........\........\..................\_primary.vhd
............\.......\.........\..........\........\...............top\verilog.psm
............\.......\.........\..........\........\..................\_primary.dat
............\.......\.........\..........\........\..................\_primary.vhd
............\.......\.........\..........\........\stimulus\verilog.psm
............\.......\.........\..........\........\........\_primary.dat
............\.......\.........\..........\........\........\_primary.vhd
............\.......\.........\..........\........\tb_clock_minmax\verilog.psm
............\.......\.........\..........\........\...............\_primary.dat
............\.......\.........\..........\........\...............\_primary.vhd
............\.......\.........\..........\........\.estbench\verilog.psm
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