ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments

Flash Memory初始化RAM实验\Project\component\PLL_1M.edn
.........................\.......\.........\work\asf\asf.sdb
.........................\.......\..nstraint\FlashinitialRAM.pdc
.........................\.......\..........\Flash_intial_RAM_main.pdc
.........................\.......\..........\main_sdc.sdc
.........................\.......\..reconsole\dfh\dfh.cci
.........................\.......\...........\...\dfh.cco
.........................\.......\...........\...\dfh.xml
.........................\.......\...........\wyq\wyq.cci
.........................\.......\...........\...\wyq.xml
.........................\.......\designer\impl1\designer.log
.........................\.......\........\.....\designer_genhdl.log
.........................\.......\........\.....\designer_gen_ba.log
.........................\.......\........\.....\flash_initial.ide_des
.........................\.......\........\.....\flash_initial.tcl
.........................\.......\........\.....\main.adb
.........................\.......\........\.....\.....dtf\verify.log
.........................\.......\........\.....\main.ide_des
.........................\.......\........\.....\main.pdb
.........................\.......\........\.....\main.pdb.depends
.........................\.......\........\.....\main.stp
.........................\.......\........\.....\main.tcl
.........................\.......\........\.....\main_ba.sdf
.........................\.......\........\.....\main_ba.v
.........................\.......\........\.....\my_ram.ide_des
.........................\.......\........\.....\my_ram.tcl
.........................\.......\........\.....\PLL_1M.ide_des
.........................\.......\........\.....\PLL_1M.tcl
.........................\.......\........\.....\send.tcl
.........................\.......\........\.....\.imulation\postlayout\main\verilog.psm
.........................\.......\........\.....\..........\..........\....\_primary.dat
.........................\.......\........\.....\..........\..........\....\_primary.vhd
.........................\.......\........\.....\..........\..........\stimulus\verilog.psm
.........................\.......\........\.....\..........\..........\........\_primary.dat
.........................\.......\........\.....\..........\..........\........\_primary.vhd
.........................\.......\........\.....\..........\..........\tb_clock_minmax\verilog.psm
.........................\.......\........\.....\..........\..........\...............\_primary.dat
.........................\.......\........\.....\..........\..........\...............\_primary.vhd
.........................\.......\........\.....\..........\..........\.estbench\verilog.psm
.........................\.......\........\.....\..........\..........\.........\_primary.dat
.........................\.......\........\.....\..........\..........\.........\_primary.vhd
.........................\.......\........\.....\..........\..........\_info
.........................\.......\hdl\control_module.v
.........................\.......\...\hdlsynchk.tcl
.........................\.......\...\main.v
.........................\.......\...\send.v
.........................\.......\...\send_control.v
.........................\.......\phy_synthesis\PLL_1M.edn
.........................\.......\RAM_module.prj
.........................\.......\simulation\flash_initial.mem
.........................\.......\..........\inilization.mem
.........................\.......\..........\modelsim.ini
.........................\.......\..........\modelsim.ini.sav
.........................\.......\..........\modelsim.log
.........................\.......\..........\my_initial_wyq.ahx
.........................\.......\..........\my_ram_block_0_my_ram_R0C0.mem
.........................\.......\..........\my_ram_R0C0.mem
.........................\.......\..........\newCore_acm_ram_R0C0.mem
.........................\.......\..........\newCore_assc_ram_R0C0.mem
.........................\.......\..........\newCore_smev_ram_R0C0.mem
.........................

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