2 choose 1 Verilog language programming environment is Quartus II 6

实验1\mux21a.asm.rpt
.....\mux21a.done
.....\mux21a.fit.rpt
.....\mux21a.fit.smsg
.....\mux21a.fit.summary
.....\mux21a.flow.rpt
.....\mux21a.map.rpt
.....\mux21a.map.summary
.....\mux21a.pin
.....\mux21a.pof
.....\mux21a.qpf
.....\mux21a.qsf
.....\mux21a.qws
.....\mux21a.sof
.....\mux21a.tan.rpt
.....\mux21a.tan.summary
.....\mux21a.v
.....\db\mux21a.asm.qmsg
.....\..\mux21a.asm_labs.ddb
.....\..\mux21a.cbx.xml
.....\..\mux21a.cmp.cdb
.....\..\mux21a.cmp.hdb
.....\..\mux21a.cmp.kpt
.....\..\mux21a.cmp.logdb
.....\..\mux21a.cmp.rdb
.....\..\mux21a.cmp.tdb
.....\..\mux21a.cmp0.ddb
.....\..\mux21a.dbp
.....\..\mux21a.db_info
.....\..\mux21a.eco.cdb
.....\..\mux21a.fit.qmsg
.....\..\mux21a.hier_info
.....\..\mux21a.hif
.....\..\mux21a.map.cdb
.....\..\mux21a.map.hdb
.....\..\mux21a.map.logdb
.....\..\mux21a.map.qmsg
.....\..\mux21a.pre_map.cdb
.....\..\mux21a.pre_map.hdb
.....\..\mux21a.psp
.....\..\mux21a.rtlv.hdb
.....\..\mux21a.rtlv_sg.cdb
.....\..\mux21a.rtlv_sg_swap.cdb
.....\..\mux21a.sgdiff.cdb
.....\..\mux21a.sgdiff.hdb
.....\..\mux21a.signalprobe.cdb
.....\..\mux21a.sld_design_entry.sci
.....\..\mux21a.sld_design_entry_dsc.sci
.....\..\mux21a.syn_hier_info
.....\..\mux21a.tan.qmsg
.....\db
实验1

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