This a FPGA project using for VGA control

VGA\atom_netlists\VGA.vqm
...\db\logic_util_heursitic.dat
...\..\prev_cmp_VGA.qmsg
...\..\VGA.amm.cdb
...\..\VGA.asm.qmsg
...\..\VGA.asm.rdb
...\..\VGA.asm_labs.ddb
...\..\VGA.cbx.xml
...\..\VGA.cdb.qmsg
...\..\VGA.cmp.bpm
...\..\VGA.cmp.cdb
...\..\VGA.cmp.hdb
...\..\VGA.cmp.kpt
...\..\VGA.cmp.logdb
...\..\VGA.cmp.rdb
...\..\VGA.cmp0.ddb
...\..\VGA.cmp1.ddb
...\..\VGA.cmp2.ddb
...\..\VGA.cmp_merge.kpt
...\..\VGA.db_info
...\..\VGA.eda.qmsg
...\..\VGA.fit.qmsg
...\..\VGA.hier_info
...\..\VGA.hif
...\..\VGA.idb.cdb
...\..\VGA.lpc.html
...\..\VGA.lpc.rdb
...\..\VGA.lpc.txt
...\..\VGA.map.bpm
...\..\VGA.map.cdb
...\..\VGA.map.hdb
...\..\VGA.map.kpt
...\..\VGA.map.logdb
...\..\VGA.map.qmsg
...\..\VGA.map_bb.cdb
...\..\VGA.map_bb.hdb
...\..\VGA.map_bb.logdb
...\..\VGA.pre_map.cdb
...\..\VGA.pre_map.hdb
...\..\VGA.rpp.qmsg
...\..\VGA.rtlv.hdb
...\..\VGA.rtlv_sg.cdb
...\..\VGA.rtlv_sg_swap.cdb
...\..\VGA.sgate.rvd
...\..\VGA.sgate_sm.rvd
...\..\VGA.sgdiff.cdb
...\..\VGA.sgdiff.hdb
...\..\VGA.sld_design_entry.sci
...\..\VGA.sld_design_entry_dsc.sci
...\..\VGA.smart_action.txt
...\..\VGA.sta.qmsg
...\..\VGA.sta.rdb
...\..\VGA.sta_cmp.8_slow.tdb
...\..\VGA.syn_hier_info
...\..\VGA.tis_db_list.ddb
...\..\VGA.tmw_info
...\greybox_tmp\cbx_args.txt
...\incremental_db\compiled_partitions\VGA.db_info
...\..............\...................\VGA.root_partition.cmp.cdb
...\..............\...................\VGA.root_partition.cmp.dfp
...\..............\...................\VGA.root_partition.cmp.hdb
...\..............\...................\VGA.root_partition.cmp.kpt
...\..............\...................\VGA.root_partition.cmp.logdb
...\..............\...................\VGA.root_partition.cmp.rcfdb
...\..............\...................\VGA.root_partition.map.cdb
...\..............\...................\VGA.root_partition.map.dpi
...\..............\...................\VGA.root_partition.map.hbdb.cdb
...\..............\...................\VGA.root_partition.map.hbdb.hb_info
...\..............\...................\VGA.root_partition.map.hbdb.hdb
...\..............\...................\VGA.root_partition.map.hbdb.sig
...\..............\...................\VGA.root_partition.map.hdb
...\..............\...................\VGA.root_partition.map.kpt
...\..............\README
...\pll.ppf
...\pll.qip
...\pll.v
...\pll_bb.v
...\simulation\modelsim\msim_transcript
...\..........\........\rtl_work\@v@g@a\_primary.dat
...\..........\........\........\......\_primary.dbs
...\..........\........\........\......\_primary.vhd
...\..........\........\........\......_@time\_primary.dat
...\..........\........\........\............\_primary.dbs
...\..........\........\........\............\_primary.vhd
...\..........\........\........\.......vlg_tst\_primary.dat
...\..........\........\........\..............\_primary.dbs
...\..........\........\........\..............\_primary.vhd
...\..........\........\........\._opt\vopt0de7xk
...\..........\........\........\.....\vopt0wwaig
...\..........\........\........\.....\vopt1g0fag
...\..........\........\........\.....\vopt1wvcch
...\..........\........\........\.....\vopt1x0img
...\..........\........\........\.....\vopt27gk1c
...\..........\........\........\.....\vopt2hms7b
...\..........\........\........\.....\vopt2meq1d
...\..........\........\........\.....\vopt30812j
...\..........\........\........\.....\vopt43h9fh
...\..........\........\........\.....\vopt4ci7ig
...\..........\........\........\.....\vopt4r44kk
...\..........\........\........\.....\vopt58qecg

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