The ram controller based on VHDL, 8 input and 8 output, a read-write control lines. Ram read and write control

ram_control_17_xian
...................\_xmsgs
...................\ram0.asy
...................\ram0.ngc
...................\ram0.sym
...................\ram0.v
...................\ram0.veo
...................\ram0.vhd
...................\ram0.vho
...................\ram0.xco
...................\ram0_flist.txt
...................\ram0_readme.txt
...................\ram0_xmdf.tcl
...................\ram_control_17_xian.ise
...................\ram_control_17_xian.restore
...................\ram_control_17_xian.vhd
...................\ram_control_17_xian_xdb
...................\.......................\tmp
...................\templates
...................\.........\coregen.xml
...................\tmp
...................\...\_cg
...................\xlnx_auto_0.ise
...................\xlnx_auto_0_xdb
...................\...............\tmp

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