verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.

EMAC6
.....\EMAC6.cgc
.....\EMAC6.cgp
.....\tmp
.....\...\_cg
.....\...\_xmsgs
.....\...\......\netgen.xmsgs
.....\...\......\ngcbuild.xmsgs
.....\...\......\pn_parser.xmsgs
.....\...\......\xst.xmsgs
.....\v6_emac_v2_1
.....\............\doc
.....\............\...\ds835_v6_emac.pdf
.....\............\...\ug800_v6_emac.pdf
.....\............\example_design
.....\............\..............\axi_ipif
.....\............\..............\........\address_decoder.v
.....\............\..............\........\axi4_lite_ipif_wrapper.v
.....\............\..............\........\axi_lite_ipif.v
.....\............\..............\........\counter_f.v
.....\............\..............\........\pselect_f.v
.....\............\..............\........\slave_attachment.v
.....\............\..............\axi_lite
.....\............\..............\........\axi_lite_sm.v
.....\............\..............\clk_wiz.v
.....\............\..............\common
.....\............\..............\......\reset_sync.v
.....\............\..............\......\sync_block.v
.....\............\..............\fifo
.....\............\..............\....\rx_client_fifo.v
.....\............\..............\....\ten_100_1g_eth_fifo.v
.....\............\..............\....\tx_client_fifo.v
.....\............\..............\pat_gen
.....\............\..............\.......\address_swap.v
.....\............\..............\.......\axi_mux.v
.....\............\..............\.......\axi_pat_check.v
.....\............\..............\.......\axi_pat_gen.v
.....\............\..............\.......\axi_pipe.v
.....\............\..............\.......\basic_pat_gen.v
.....\............\..............\physical
.....\............\..............\........\gmii_if.v
.....\............\..............\statistics
.....\............\..............\..........\vector_decode.v
.....\............\..............\v6_emac_v2_1_block.v
.....\............\..............\v6_emac_v2_1_example_design.ucf
.....\............\..............\v6_emac_v2_1_example_design.v
.....\............\..............\v6_emac_v2_1_fifo_block.v
.....\............\..............\v6_emac_v2_1_mod.v
.....\............\implement
.....\............\.........\implement.bat
.....\............\.........\implement.sh
.....\............\.........\xst.prj
.....\............\.........\xst.scr
.....\............\simulation
.....\............\..........\demo_tb.v
.....\............\..........\functional
.....\............\..........\..........\simulate_mti.do
.....\............\..........\..........\simulate_ncsim.sh
.....\............\..........\..........\simulate_vcs.sh
.....\............\..........\..........\ucli_commands.key
.....\............\..........\..........\vcs_session.tcl
.....\............\..........\..........\wave_mti.do
.....\............\..........\..........\wave_ncsim.sv
.....\............\..........\mdio_tb.v
.....\............\..........\phy_tb.v
.....\............\..........\timing
.....\............\..........\......\simulate_mti.do
.....\............\..........\......\simulate_ncsim.sh
.....\............\..........\......\simulate_vcs.sh
.....\............\..........\......\ucli_commands.key
.....\............\..........\......\vcs_session.tcl
.....\............\..........\......\wave_mti.do
.....\............\..........\......\wave_ncsim.sv
.....\............\v6_emac_readme.txt
.....\v6_emac_v2_1.asy
.....\v6_emac_v2_1.gise
.....\v6_emac_v2_1.ngc
.....\v6_emac_v2_1.v
.....\v6_emac_v2_1.veo
.....\v6_emac_v2_1.xco
.....\v6_emac_v2_1.xise
.....\v6_emac_v2_1_emac_wrapper_1.lso
.....\v6_emac_v2_1_flist.txt
.....\v6_emac_v2_1_xmdf.tcl
.....\xlnx_auto_0_xdb

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