vhdl using the dual-port RAM, compiled by engineering.

DUAL-PORT-RAM\db\altsyncram_1ep3.tdf
.............\..\altsyncram_3bp3.tdf
.............\..\altsyncram_9b82.tdf
.............\..\altsyncram_b7p3.tdf
.............\..\altsyncram_bdp3.tdf
.............\..\altsyncram_d7p3.tdf
.............\..\altsyncram_pap3.tdf
.............\..\altsyncram_rap3.tdf
.............\..\altsyncram_tap3.tdf
.............\..\altsyncram_vdp3.tdf
.............\..\cmpr_efc.tdf
.............\..\cmpr_hfc.tdf
.............\..\cmpr_ifc.tdf
.............\..\cmpr_jfc.tdf
.............\..\cmpr_kfc.tdf
.............\..\cmpr_lfc.tdf
.............\..\cntr_0hi.tdf
.............\..\cntr_3fi.tdf
.............\..\cntr_4fi.tdf
.............\..\cntr_5fi.tdf
.............\..\cntr_6fi.tdf
.............\..\cntr_78j.tdf
.............\..\cntr_7aj.tdf
.............\..\cntr_8fi.tdf
.............\..\cntr_9fi.tdf
.............\..\cntr_afi.tdf
.............\..\cntr_f8j.tdf
.............\..\cntr_ffi.tdf
.............\..\cntr_kgi.tdf
.............\..\cntr_p1j.tdf
.............\..\cntr_v7j.tdf
.............\..\cntr_vgi.tdf
.............\..\decode_4uf.tdf
.............\..\decode_dra.tdf
.............\..\IOCtlLogic.asm.qmsg
.............\..\IOCtlLogic.asm_labs.ddb
.............\..\IOCtlLogic.cbx.xml
.............\..\IOCtlLogic.cmp.bpm
.............\..\IOCtlLogic.cmp.cdb
.............\..\IOCtlLogic.cmp.ecobp
.............\..\IOCtlLogic.cmp.hdb
.............\..\IOCtlLogic.cmp.kpt
.............\..\IOCtlLogic.cmp.logdb
.............\..\IOCtlLogic.cmp.rdb
.............\..\IOCtlLogic.cmp_merge.kpt
.............\..\IOCtlLogic.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.............\..\IOCtlLogic.cuda_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
.............\..\IOCtlLogic.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.............\..\IOCtlLogic.db_info
.............\..\IOCtlLogic.eco.cdb
.............\..\IOCtlLogic.fit.qmsg
.............\..\IOCtlLogic.hier_info
.............\..\IOCtlLogic.hif
.............\..\IOCtlLogic.lpc.html
.............\..\IOCtlLogic.lpc.rdb
.............\..\IOCtlLogic.lpc.txt
.............\..\IOCtlLogic.map.bpm
.............\..\IOCtlLogic.map.cdb
.............\..\IOCtlLogic.map.ecobp
.............\..\IOCtlLogic.map.hdb
.............\..\IOCtlLogic.map.kpt
.............\..\IOCtlLogic.map.logdb
.............\..\IOCtlLogic.map.qmsg
.............\..\IOCtlLogic.map.rcf
.............\..\IOCtlLogic.map_bb.cdb
.............\..\IOCtlLogic.map_bb.hdb
.............\..\IOCtlLogic.map_bb.logdb
.............\..\IOCtlLogic.merge.qmsg
.............\..\IOCtlLogic.pre_map.cdb
.............\..\IOCtlLogic.pre_map.hdb
.............\..\IOCtlLogic.rpp.qmsg
.............\..\IOCtlLogic.rtlv.hdb
.............\..\IOCtlLogic.rtlv_sg.cdb
.............\..\IOCtlLogic.rtlv_sg_swap.cdb
.............\..\IOCtlLogic.sgate.rvd
.............\..\IOCtlLogic.sgate_sm.rvd
.............\..\IOCtlLogic.sgdiff.cdb
.............\..\IOCtlLogic.sgdiff.hdb
.............\..\IOCtlLogic.sld_design_entry.sci
.............\..\IOCtlLogic.sld_design_entry_dsc.sci
.............\..\IOCtlLogic.sta.qmsg
.............\..\IOCtlLogic.sta.rdb
.............\..\IOCtlLogic.sta_cmp.7_slow_1200mv_85c.tdb
.............\..\IOCtlLogic.syn_hier_info
.............\..\IOCtlLogic.tiscmp.fastest_slow_1200mv_0c.ddb
.............\..\IOCtlLogic.tiscmp.fastest_slow_1200mv_85c.ddb
.............\..\IOCtlLogic.tiscmp.fast_1200mv_0c.ddb
.............\..\IOCtlLogic.tiscmp.slow_1200mv_0c.ddb
.............\..\IOCtlLogic.tiscmp.slow_1200mv_85c.ddb
.............\..\IOCtlLogic.tis_db_list.ddb
.............\..\IOCtlLogic.tmw_info
.............\..\IOCtlLogic_global_asgn_op.abo
.............\..\mux_9nb.tdf
.............\..\mux_grc.tdf
.............\..\mux_hrc.tdf
.............\..\mux_irc.tdf
.............\..\mux_mrc.tdf
.............\..\prev_cmp_IOCtlLogic.asm.qmsg
.............\..\prev_cmp_IOCtlLogic.fit.qmsg
.............\..\prev_cmp_IOCtlLogic.map.qmsg

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