A Complete Multicycle CPU Written in Verilog Lang.

ALU.v
Aluoc.v
ami.v
ContorlUnit.v
CPU.v
cputest.v
cputesttt.v
cpuutest.v
gf.v
MemoryIns.v
memorytest.v
memtest.v
Mux2to1.v
Mux3to1.v
Mux3to1_32.v
Mux4to1.v
PC.v
PcFirst.v
PCPlus.v
REGISTER_file_test.v
register_test.v
RegisterFile.v
s.v
Sabbat.v
SabbatCond.v
sd.v
sign_test.v
SignExtended.v
SignW.v
Test_SignExtended.v
TestRF.v
Adder.v

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