Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim

CPU_test\accum.v
........\addr_decode.v
........\adr.v
........\alu.v
........\clk_gen.v
........\counter.v
........\cpu.v
........\cpu.v.bak
........\CPU_RISC.mpf
........\datactl.v
........\machine.v
........\machinect1.v.bak
........\machinectl.v
........\ram.v
........\register.v
........\RISC_CPU.cr.mti
........\RISC_CPU.mpf
........\rom.v
........\test1.dat
........\test1.dat.bak
........\test1.pro.bak
........\test1.txt
........\test1_data.txt
........\test2.dat
........\test2.txt
........\test2_data.txt
........\test3.dat
........\test3.txt
........\test3_data.txt
........\test_cpu.v
........\test_cpu.v.bak
........\vsim.wlf
........\work\accum\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\.ddr_decode\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\..r\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\.lu\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\clk_gen\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.ounter\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.pu\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\datactl\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\machine\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\.......ctl\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\ram\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\.egister\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\.om\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.vhd
........\....\test_cpu\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\_info
........\....\.opt\work_accum_fast.dt2
........\....\....\work_addr_decode_fast.dt2
........\....\....\work_adr_fast.asm
........\....\....\work_adr_fast.dt2
........\....\....\work_alu_fast.asm
........\....\....\work_alu_fast.dt2
........\....\....\work_clk_gen_fast.dt2
........\....\....\work_counter_fast.dt2
........\....\....\work_cpu_fast.dt2
........\....\....\work_datactl_fast.dt2
........\....\....\work_machinectl_fast.dt2
........\....\....\work_machine_fast.dt2
........\....\....\work_ram_fast.dt2
........\....\....\work_register_fast.dt2
........\....\....\work_rom_fast.dt2
........\....\....\work_test_cpu_fast.asm
........\....\....\work_test_cpu_fast.dt2
........\....\....\work__info
........\....\....\_deps
........\....\accum
........\....\addr_decode
........\....\adr
........\....\alu
........\....\clk_gen
........\....\counter

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．