this a 32 bit cpu designer project,which use verilog language. Hope it could help u.

final
.....\alu.v
.....\clk_gen.v
.....\cycloneii_atoms.v
.....\dmem.v
.....\ID.v
.....\IE.v
.....\IF.v
.....\imem.v
.....\MiniRisc_top.v
.....\multi_flag_ctrl.v
.....\register.v
.....\reg_dmem_rw.v
.....\risc.cr.mti
.....\risc.mpf
.....\sign_extend.v
.....\test_bench2.v
.....\top_module.v
.....\vsim.wlf
.....\work
.....\....\@a@l@u
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e
.....\....\....................................\verilog.asm
.....\....\....................................\_primary.dat
.....\....\....................................\_primary.vhd
.....\....\@i@d
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\@i@e
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\@i@f
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\@mini@risc_@c@p@u
.....\....\.................\verilog.asm
.....\....\.................\_primary.dat
.....\....\.................\_primary.vhd
.....\....\@mini@risc_top
.....\....\..............\verilog.asm
.....\....\..............\_primary.dat
.....\....\..............\_primary.vhd
.....\....\clk_gen
.....\....\.......\verilog.asm
.....\....\.......\_primary.dat
.....\....\.......\_primary.vhd
.....\....\cycloneii_and1
.....\....\cycloneii_and16
.....\....\...............\verilog.asm
.....\....\...............\_primary.dat
.....\....\...............\_primary.vhd
.....\....\..............\verilog.asm
.....\....\..............\_primary.dat
.....\....\..............\_primary.vhd
.....\....\cycloneii_asmiblock
.....\....\...................\verilog.asm
.....\....\...................\_primary.dat
.....\....\...................\_primary.vhd
.....\....\cycloneii_asynch_io
.....\....\...................\verilog.asm
.....\....\...................\_primary.dat
.....\....\...................\_primary.vhd
.....\....\cycloneii_b17mux21
.....\....\..................\verilog.asm
.....\....\..................\_primary.dat
.....\....\..................\_primary.vhd
.....\....\cycloneii_b5mux21
.....\....\.................\verilog.asm
.....\....\.................\_primary.dat
.....\....\.................\_primary.vhd
.....\....\cycloneii_bmux21
.....\....\................\verilog.asm
.....\....\................\_primary.dat
.....\....\................\_primary.vhd
.....\....\cycloneii_clkctrl
.....\....\.................\verilog.asm
.....\....\.................\_primary.dat
.....\....\.................\_primary.vhd
.....\....\cycloneii_clk_delay_cal_ctrl
.....\....\............................\verilog.asm
.....\....\............................\_primary.dat
.....\....\............................\_primary.vhd
.....\....\cycloneii_clk_delay_ctrl
.....\....\........................\verilog.asm
.....\....\........................\_primary.dat
.....\....\........................\_primary.vhd
.....\....\cycloneii_crcblock
.....\....\..................\verilog.asm
.....\....\..................\_primary.dat
.....\....\..................\_primary.vhd
.....\....\cycloneii_dffe
.....\....\..............\verilog.asm
.....\....\..............\_primary.dat
.....\....\..............\_primary.vhd

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