risc_cpu ,verilog ,have passd

risc_cpu_619
............\accum.v
............\addr_decode.v
............\adr.v
............\alu.v
............\clk_gen.v
............\counter.v
............\cpu.v
............\cputop.v
............\cputop_rtl.v
............\datactl.v
............\machine.v
............\machinectl.v
............\modelsim.ini
............\ram.v
............\register.v
............\rom.v
............\test1.dat
............\test1.pro
............\test1.pro.old
............\test2.dat
............\test2.pro
............\test3.dat
............\test3.pro
............\transcript
............\vsim.wlf
............\wlfthegkaq
............\work
............\....\_info
............\....\_temp
............\....\.....\vlog4afnmx
............\....\.....\vloga07grn
............\....\.....\vlogbvtz07
............\....\_vmake
............\....\accum
............\....\.....\_primary.dat
............\....\.....\_primary.dbs
............\....\.....\_primary.vhd
............\....\.....\verilog.asm
............\....\.....\verilog.rw
............\....\addr_decode
............\....\...........\_primary.dat
............\....\...........\_primary.dbs
............\....\...........\_primary.vhd
............\....\...........\verilog.asm
............\....\...........\verilog.rw
............\....\adr
............\....\...\_primary.dat
............\....\...\_primary.dbs
............\....\...\_primary.vhd
............\....\...\verilog.asm
............\....\...\verilog.rw
............\....\alu
............\....\...\_primary.dat
............\....\...\_primary.dbs
............\....\...\_primary.vhd
............\....\...\verilog.asm
............\....\...\verilog.rw
............\....\clk_gen
............\....\.......\_primary.dat
............\....\.......\_primary.dbs
............\....\.......\_primary.vhd
............\....\.......\verilog.asm
............\....\.......\verilog.rw
............\....\counter
............\....\.......\_primary.dat
............\....\.......\_primary.dbs
............\....\.......\_primary.vhd
............\....\.......\verilog.asm
............\....\.......\verilog.rw
............\....\cpu
............\....\...\_primary.dat
............\....\...\_primary.dbs
............\....\...\_primary.vhd
............\....\...\verilog.asm
............\....\...\verilog.rw
............\....\cputop
............\....\......\_primary.dat
............\....\......\_primary.dbs
............\....\......\_primary.vhd
............\....\......\verilog.asm
............\....\......\verilog.rw
............\....\datactl
............\....\.......\_primary.dat
............\....\.......\_primary.dbs
............\....\.......\_primary.vhd
............\....\.......\verilog.asm
............\....\.......\verilog.rw
............\....\machine
............\....\.......\_primary.dat
............\....\.......\_primary.dbs
............\....\.......\_primary.vhd
............\....\.......\verilog.asm
............\....\.......\verilog.rw
............\....\machinectl
............\....\..........\_primary.dat
............\....\..........\_primary.dbs
............\....\..........\_primary.vhd
............\....\..........\verilog.asm
............\....\..........\verilog.rw

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