Recommended clock using Verilog language, and through the buttons configuration clock.

Clock_module
............\Clock_module.asm.rpt
............\Clock_module.cdf
............\Clock_module.done
............\Clock_module.dpf
............\Clock_module.eda.rpt
............\Clock_module.fit.rpt
............\Clock_module.fit.smsg
............\Clock_module.fit.summary
............\Clock_module.flow.rpt
............\Clock_module.jdi
............\Clock_module.map.rpt
............\Clock_module.map.smsg
............\Clock_module.map.summary
............\Clock_module.pin
............\Clock_module.pof
............\Clock_module.qpf
............\Clock_module.qsf
............\Clock_module.qws
............\Clock_module.sof
............\Clock_module.tan.rpt
............\Clock_module.tan.summary
............\Clock_module.v
............\Clock_module.v.bak
............\Counter_module
............\..............\Counter_module.v
............\..............\Counter_module.v.bak
............\Key_Interface
............\.............\debounce_module2.v
............\.............\debounce_module2.v.bak
............\.............\delay_module.v
............\.............\detect_module.v
............\.............\transcript
............\Menu_Interface
............\..............\Menu_module.v
............\..............\Menu_module.v.bak
............\SMG_module
............\..........\SMG_interface.v
............\..........\SMG_interface.v.bak
............\..........\number_mod_module.v
............\..........\number_mod_module.v.bak
............\..........\smg_encoder_module
............\..........\..................\smg_encoder_module.v
............\..........\..................\smg_encoder_module.v.bak
............\..........\smg_scan_module
............\..........\...............\smg_scan_module.v
............\..........\...............\smg_scan_module.v.bak
............\db
............\..\Clock_module.asm.qmsg
............\..\Clock_module.asm_labs.ddb
............\..\Clock_module.cbx.xml
............\..\Clock_module.cmp.bpm
............\..\Clock_module.cmp.cdb
............\..\Clock_module.cmp.ecobp
............\..\Clock_module.cmp.hdb
............\..\Clock_module.cmp.kpt
............\..\Clock_module.cmp.logdb
............\..\Clock_module.cmp.rdb
............\..\Clock_module.cmp.tdb
............\..\Clock_module.cmp0.ddb
............\..\Clock_module.cmp2.ddb
............\..\Clock_module.cmp_merge.kpt
............\..\Clock_module.db_info
............\..\Clock_module.eco.cdb
............\..\Clock_module.eda.qmsg
............\..\Clock_module.fit.qmsg
............\..\Clock_module.hier_info
............\..\Clock_module.hif
............\..\Clock_module.lpc.html
............\..\Clock_module.lpc.rdb
............\..\Clock_module.lpc.txt
............\..\Clock_module.map.bpm
............\..\Clock_module.map.cdb
............\..\Clock_module.map.ecobp
............\..\Clock_module.map.hdb
............\..\Clock_module.map.kpt
............\..\Clock_module.map.logdb
............\..\Clock_module.map.qmsg
............\..\Clock_module.map_bb.cdb
............\..\Clock_module.map_bb.hdb
............\..\Clock_module.map_bb.logdb
............\..\Clock_module.pre_map.cdb
............\..\Clock_module.pre_map.hdb
............\..\Clock_module.rpp.qmsg
............\..\Clock_module.rtlv.hdb
............\..\Clock_module.rtlv_sg.cdb
............\..\Clock_module.rtlv_sg_swap.cdb
............\..\Clock_module.sgate.rvd
............\..\Clock_module.sgate_sm.rvd
............\..\Clock_module.sgdiff.cdb
............\..\Clock_module.sgdiff.hdb
............\..\Clock_module.sld_design_entry.sci
............\..\Clock_module.sld_design_entry_dsc.sci
............\..\Clock_module.smp_dump.txt
............\..\Clock_module.syn_hier_info
............\..\Clock_module.tan.qmsg
............\..\Clock_module.tis_db_list.ddb
............\..\Clock_module_global_asgn_op.abo
............\..\add_sub_lkc.tdf
............\..\add_sub_mkc.tdf

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