xilin Zynq Digilent Zedboard official data summary of, development Zedboard essential

cf_adv7511_zed\data\ps7_constraints.ucf
..............\....\ps7_constraints.xdc
..............\....\ps7_system_prj.xml
..............\....\system.ucf
..............\license.txt
..............\sw\cf_adv7511_zed.bit
..............\..\cf_adv7511_zed.c
..............\..\cf_adv7511_zed.elf
..............\..\cf_adv7511_zed.h
..............\..\cf_adv7511_zed.tcl
..............\..\ps7_init.tcl
..............\system.mhs
..............\system.xmp
...lib\edk\pcores\axi_clkgen_v1_00_a\data\axi_clkgen_v2_1_0.mpd
......\...\......\..................\....\axi_clkgen_v2_1_0.pao
......\...\......\..................\....\_axi_clkgen_xst.prj
......\...\......\..................\hdl\verilog\cf_clkgen.v
......\...\......\..................\...\.......\user_logic.v
......\...\......\..................\...\.hdl\axi_clkgen.vhd
......\...\......\..................\regmap.txt
......\...\......\....hdmi_tx_16b_v1_00_a\data\axi_hdmi_tx_16b_v2_1_0.mpd
......\...\......\.......................\....\axi_hdmi_tx_16b_v2_1_0.pao
......\...\......\.......................\....\_axi_hdmi_tx_16b_xst.prj
......\...\......\.......................\hdl\verilog\cf_add.v
......\...\......\.......................\...\.......\cf_csc_1.v
......\...\......\.......................\...\.......\cf_csc_RGB2CrYCb.v
......\...\......\.......................\...\.......\cf_hdmi.v
......\...\......\.......................\...\.......\cf_hdmi_tx_16b.v
......\...\......\.......................\...\.......\cf_mem.v
......\...\......\.......................\...\.......\cf_mul.v
......\...\......\.......................\...\.......\cf_ss_444to422.v
......\...\......\.......................\...\.......\cf_vdma.v
......\...\......\.......................\...\.......\user_logic.v
......\...\......\.......................\...\.hdl\axi_hdmi_tx_16b.vhd
......\...\......\.......................\regmap.txt
......\...\......\....spdif_tx_v1_00_a\data\axi_spdif_tx_v2_1_0.mpd
......\...\......\....................\....\axi_spdif_tx_v2_1_0.pao
......\...\......\....................\....\_axi_spdif_tx_xst.prj
......\...\......\....................\hdl\vhdl\axi_spdif_tx.vhd
......\...\......\....................\...\....\tx_bitbuf.vhd
......\...\......\....................\...\....\tx_encoder.vhd
......\...\......\....................\...\....\tx_package.vhd
......\...\......\....................\...\....\user_logic.vhd
......\...\......\....clkgen_v1_00_a\hdl\verilog
......\...\......\..................\...\vhdl
......\...\......\....hdmi_tx_16b_v1_00_a\hdl\verilog
......\...\......\.......................\...\vhdl
......\...\......\....spdif_tx_v1_00_a\hdl\vhdl
......\...\......\....clkgen_v1_00_a\data
......\...\......\..................\hdl
......\...\......\....hdmi_tx_16b_v1_00_a\data
......\...\......\.......................\hdl
......\...\......\....spdif_tx_v1_00_a\data
......\...\......\....................\hdl
......\...\......\axi_clkgen_v1_00_a
......\...\......\axi_hdmi_tx_16b_v1_00_a
......\...\......\axi_spdif_tx_v1_00_a
......\...\pcores
...adv7511_zed\data
..............\sw
...lib\edk
cf_adv7511_zed
cf_lib

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