CPLD Verilog HDL digital clock

digital clock\clkgen.bsf
.............\clkgen.v
.............\clkgen.v.bak
.............\clock.bsf
.............\clock.qpf
.............\clock.qws
.............\clock.v
.............\clock.v.bak
.............\cmp_state.ini
.............\db\prev_cmp_clock.qmsg
.............\..\prev_cmp_top.asm.qmsg
.............\..\prev_cmp_top.fit.qmsg
.............\..\prev_cmp_top.map.qmsg
.............\..\prev_cmp_top.tan.qmsg
.............\..\top.db_info
.............\..\top.eco.cdb
.............\..\top.sld_design_entry.sci
.............\..\top_cmp.qrpt
.............\top.asm.rpt
.............\top.bsf
.............\top.cdf
.............\top.done
.............\top.dpf
.............\top.fit.eqn
.............\top.fit.rpt
.............\top.fit.smsg
.............\top.fit.summary
.............\top.flow.rpt
.............\top.map.eqn
.............\top.map.rpt
.............\top.map.summary
.............\top.pin
.............\top.pof
.............\top.qsf
.............\top.sof
.............\top.tan.rpt
.............\top.tan.summary
.............\top.v
.............\top.v.bak
.............\top_assignment_defaults.qdf
.............\db
digital clock

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