FPGA DDS algorithm Verilog program implementation

FPGA DDS algorithm\newdds\dds\acc.v
..................\......\...\cmp_state.ini
..................\......\...\db\accum_3lh.tdf
..................\......\...\..\add_sub_21h.tdf
..................\......\...\..\add_sub_31h.tdf
..................\......\...\..\add_sub_44h.tdf
..................\......\...\..\add_sub_pbg.tdf
..................\......\...\..\add_sub_rod.tdf
..................\......\...\..\altsyncram_0ps.tdf
..................\......\...\..\altsyncram_3ru.tdf
..................\......\...\..\altsyncram_8ru.tdf
..................\......\...\..\altsyncram_auu.tdf
..................\......\...\..\altsyncram_j5q.tdf
..................\......\...\..\altsyncram_pfq.tdf
..................\......\...\..\altsyncram_ros.tdf
..................\......\...\..\altsyncram_ufq.tdf
..................\......\...\..\cntr_0gc.tdf
..................\......\...\..\cntr_2gc.tdf
..................\......\...\..\cntr_e08.tdf
..................\......\...\..\cntr_sv7.tdf
..................\......\...\..\dds.db_info
..................\......\...\..\dds.sim.vwf
..................\......\...\..\dds_cmp.qrpt
..................\......\...\..\dds_sim.qrpt
..................\......\...\..\decode_bje.tdf
..................\......\...\..\mux_gdb.tdf
..................\......\...\..\shift_taps_6lg.tdf
..................\......\...\..\shift_taps_7lg.tdf
..................\......\...\dds.asm.rpt
..................\......\...\dds.cdf
..................\......\...\dds.done
..................\......\...\dds.eda.rpt
..................\......\...\dds.fit.eqn
..................\......\...\dds.fit.rpt
..................\......\...\dds.fit.summary
..................\......\...\dds.flow.rpt
..................\......\...\dds.map.eqn
..................\......\...\dds.map.rpt
..................\......\...\dds.map.summary
..................\......\...\dds.pin
..................\......\...\dds.pof
..................\......\...\dds.qpf
..................\......\...\dds.qsf
..................\......\...\dds.sim.rpt
..................\......\...\dds.sof
..................\......\...\dds.tan.rpt
..................\......\...\dds.tan.summary
..................\......\...\dds.vwf
..................\......\...\ddsrom.v
..................\......\...\ddsromcos.mif
..................\......\...\ddsromcos.v
..................\......\...\ddsromsin.mif
..................\......\...\ddsromsin.v
..................\......\...\ddsromsin.ver
..................\......\...\dds_adder.v
..................\......\...\dds_assignment_defaults.qdf
..................\......\...\dds_test.cr.mti
..................\......\...\dds_test.mpf
..................\......\...\dds_test.tcl
..................\......\...\dds_testmodsim.do
..................\......\...\dds_testmodsim.v
..................\......\...\dds_time_limited.sof
..................\......\...\ipnco.bsf
..................\......\...\ipnco.cmp
..................\......\...\ipnco.html
..................\......\...\ipnco.inc
..................\......\...\ipnco.v
..................\......\...\ipnco.vec
..................\......\...\ipnco.vo
..................\......\...\ipnco_bb.v
..................\......\...\ipnco_cos.hex
..................\......\...\ipnco_cos.mif
..................\......\...\ipnco_cos.v
..................\......\...\ipnco_inst.v
..................\......\...\ipnco_model.m
..................\......\...\ipnco_sin.hex
..................\......\...\ipnco_sin.mif
..................\......\...\ipnco_sin.v
..................\......\...\ipnco_st.inc
..................\......\...\ipnco_st.v
..................\......\...\ipnco_tb.m
..................\......\...\ipnco_tb.v
..................\......\...\ipnco_tb.vhd
..................\......\...\ipnco_vho_msim.tcl
..................\......\...\ipnco_vo_msim.tcl
..................\......\...\ipnco_wave.do
..................\......\...\mytest.cr.mti
..................\......\...\mytest.mpf
..................\......\...\newdds.v
..................\......\...\newdds_baking.v
..................\......\...\pllx.v
..................\......\...\sim.cfg
..................\......

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