the verilog hdl write a serial program, compile simulation have passed

tx\db\logic_util_heursitic.dat
..\..\prev_cmp_tx.qmsg
..\..\tx.amm.cdb
..\..\tx.asm.qmsg
..\..\tx.asm.rdb
..\..\tx.asm_labs.ddb
..\..\tx.cbx.xml
..\..\tx.cmp.bpm
..\..\tx.cmp.cdb
..\..\tx.cmp.hdb
..\..\tx.cmp.kpt
..\..\tx.cmp.logdb
..\..\tx.cmp.rdb
..\..\tx.cmp_merge.kpt
..\..\tx.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
..\..\tx.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
..\..\tx.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
..\..\tx.db_info
..\..\tx.eda.qmsg
..\..\tx.fit.qmsg
..\..\tx.hier_info
..\..\tx.hif
..\..\tx.idb.cdb
..\..\tx.lpc.html
..\..\tx.lpc.rdb
..\..\tx.lpc.txt
..\..\tx.map.bpm
..\..\tx.map.cdb
..\..\tx.map.hdb
..\..\tx.map.kpt
..\..\tx.map.logdb
..\..\tx.map.qmsg
..\..\tx.map_bb.cdb
..\..\tx.map_bb.hdb
..\..\tx.map_bb.logdb
..\..\tx.pre_map.cdb
..\..\tx.pre_map.hdb
..\..\tx.root_partition.map.reg_db.cdb
..\..\tx.rtlv.hdb
..\..\tx.rtlv_sg.cdb
..\..\tx.rtlv_sg_swap.cdb
..\..\tx.sgdiff.cdb
..\..\tx.sgdiff.hdb
..\..\tx.sld_design_entry.sci
..\..\tx.sld_design_entry_dsc.sci
..\..\tx.smart_action.txt
..\..\tx.sta.qmsg
..\..\tx.sta.rdb
..\..\tx.sta_cmp.8_slow_1200mv_85c.tdb
..\..\tx.syn_hier_info
..\..\tx.tiscmp.fastest_slow_1200mv_0c.ddb
..\..\tx.tiscmp.fastest_slow_1200mv_85c.ddb
..\..\tx.tiscmp.fast_1200mv_0c.ddb
..\..\tx.tiscmp.slow_1200mv_0c.ddb
..\..\tx.tiscmp.slow_1200mv_85c.ddb
..\..\tx.tis_db_list.ddb
..\..\tx.tmw_info
..\incremental_db\compiled_partitions\tx.db_info
..\..............\...................\tx.root_partition.cmp.cdb
..\..............\...................\tx.root_partition.cmp.dfp
..\..............\...................\tx.root_partition.cmp.hdb
..\..............\...................\tx.root_partition.cmp.kpt
..\..............\...................\tx.root_partition.cmp.logdb
..\..............\...................\tx.root_partition.cmp.rcfdb
..\..............\...................\tx.root_partition.map.cdb
..\..............\...................\tx.root_partition.map.dpi
..\..............\...................\tx.root_partition.map.hbdb.cdb
..\..............\...................\tx.root_partition.map.hbdb.hb_info
..\..............\...................\tx.root_partition.map.hbdb.hdb
..\..............\...................\tx.root_partition.map.hbdb.sig
..\..............\...................\tx.root_partition.map.hdb
..\..............\...................\tx.root_partition.map.kpt
..\..............\README
..\simulation\modelsim\modelsim.ini
..\..........\........\msim_transcript
..\..........\........\rtl_work\tx\verilog.prw
..\..........\........\........\..\verilog.psm
..\..........\........\........\..\_primary.dat
..\..........\........\........\..\_primary.dbs
..\..........\........\........\..\_primary.vhd
..\..........\........\........\.._bps_module\verilog.prw
..\..........\........\........\.............\verilog.psm
..\..........\........\........\.............\_primary.dat
..\..........\........\........\.............\_primary.dbs
..\..........\........\........\.............\_primary.vhd
..\..........\........\........\...control_module\verilog.prw
..\..........\........\........\.................\verilog.psm
..\..........\........\........\.................\_primary.dat
..\..........\........\........\.................\_primary.dbs
..\..........\........\........\.................\_primary.vhd
..\..........\........\........\...tn\verilog.prw
..\..........\........\........\.....\verilog.psm
..\..........\........\........\.....\_primary.dat
..\..........\........\........\.....\_primary.dbs
..\..........\........\........\.....\_primary.vhd
..\..........\........\........\_info
..\..........\........\........\_vmake
..\..........\........\tx.sft
..\..........\........\tx.vo
..\..........\........\tx_8_1200mv_0c_slow.vo

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