design the quartus under the DDS source, can achieve a variety of waveforms of different frequencies and amplitude switching, friendly interface.

DDS_total
.........\DDS_HAO
.........\DDS_HAO.BIN
.........\DDS_HAO.C
.........\DDS_HAO.HEX
.........\DDS_HAO.LST
.........\DDS_HAO.M51
.........\DDS_HAO.OBJ
.........\Hex1.hex
.........\Hex1.qpf
.........\Hex1.qsf
.........\TEMP.LST
.........\WAVE.LIN
.........\add373.bsf
.........\add373.inc
.........\add373.v
.........\buffer.bsf
.........\buffer.v
.........\bus_connect.bsf
.........\bus_connect.v
.........\count.bsf
.........\count.v
.........\db
.........\..\altsyncram_5t21.tdf
.........\..\altsyncram_dt21.tdf
.........\..\altsyncram_etp1.tdf
.........\..\altsyncram_f831.tdf
.........\..\altsyncram_j331.tdf
.........\..\altsyncram_sd61.tdf
.........\..\altsyncram_vsl1.tdf
.........\..\dds_verilog.asm.qmsg
.........\..\dds_verilog.cbx.xml
.........\..\dds_verilog.cmp.bpm
.........\..\dds_verilog.cmp.cdb
.........\..\dds_verilog.cmp.ecobp
.........\..\dds_verilog.cmp.hdb
.........\..\dds_verilog.cmp.logdb
.........\..\dds_verilog.cmp.rdb
.........\..\dds_verilog.cmp.tdb
.........\..\dds_verilog.cmp0.ddb
.........\..\dds_verilog.cmp_bb.cdb
.........\..\dds_verilog.cmp_bb.hdb
.........\..\dds_verilog.cmp_bb.logdb
.........\..\dds_verilog.cmp_bb.rcf
.........\..\dds_verilog.db_info
.........\..\dds_verilog.dbp
.........\..\dds_verilog.eco.cdb
.........\..\dds_verilog.fit.qmsg
.........\..\dds_verilog.hier_info
.........\..\dds_verilog.hif
.........\..\dds_verilog.map.bpm
.........\..\dds_verilog.map.cdb
.........\..\dds_verilog.map.ecobp
.........\..\dds_verilog.map.hdb
.........\..\dds_verilog.map.logdb
.........\..\dds_verilog.map.qmsg
.........\..\dds_verilog.map_bb.cdb
.........\..\dds_verilog.map_bb.hdb
.........\..\dds_verilog.map_bb.logdb
.........\..\dds_verilog.pre_map.cdb
.........\..\dds_verilog.pre_map.hdb
.........\..\dds_verilog.psp
.........\..\dds_verilog.pss
.........\..\dds_verilog.rtlv.hdb
.........\..\dds_verilog.rtlv_sg.cdb
.........\..\dds_verilog.rtlv_sg_swap.cdb
.........\..\dds_verilog.sgdiff.cdb
.........\..\dds_verilog.sgdiff.hdb
.........\..\dds_verilog.signalprobe.cdb
.........\..\dds_verilog.sld_design_entry.sci
.........\..\dds_verilog.sld_design_entry_dsc.sci
.........\..\dds_verilog.syn_hier_info
.........\..\dds_verilog.tan.qmsg
.........\..\dds_verilog.tis_db_list.ddb
.........\..\prev_cmp_dds_verilog.asm.qmsg
.........\..\prev_cmp_dds_verilog.fit.qmsg
.........\..\prev_cmp_dds_verilog.map.qmsg
.........\..\prev_cmp_dds_verilog.qmsg
.........\..\prev_cmp_dds_verilog.tan.qmsg
.........\dds.bdf
.........\dds_verilog.asm.rpt
.........\dds_verilog.cdf
.........\dds_verilog.done
.........\dds_verilog.dpf
.........\dds_verilog.fit.rpt
.........\dds_verilog.fit.smsg
.........\dds_verilog.fit.summary
.........\dds_verilog.flow.rpt
.........\dds_verilog.map.rpt
.........\dds_verilog.map.smsg
.........\dds_verilog.map.summary
.........\dds_verilog.pin
.........\dds_verilog.pof
.........\dds_verilog.qpf
.........\dds_verilog.qsf
.........\dds_verilog.sof
.........\dds_verilog.tan.rpt
.........\dds_verilog.tan.summary
.........\fenpin.bsf
.........\fenpin.v

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