PIC10 CPU IP Core Verilog Implementation reference:John Gulbrandsen 《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》

pic10_verilog\PIC10F.pdf
.............\PIC10F200_单片机IP核的实现.pdf
.............\pic10_alu.v
.............\pic10_alu_datapath.v
.............\pic10_alu_mux.v
.............\pic10_controller.v
.............\pic10_cpu.v
.............\pic10_datapath.v
.............\pic10_fsr.v
.............\pic10_gpio_reg.v
.............\pic10_ir.v
.............\pic10_pc.v
.............\pic10_pc_datapath.v
.............\pic10_pc_mux.v
.............\pic10_program_mux.v
.............\pic10_program_store.v
.............\pic10_ram_registers.v
.............\pic10_ram_sfr_datapath.v
.............\pic10_register_address_mux.v
.............\PIC10_RISC_Design.pdf
.............\pic10_sfr_data_mux.v
.............\pic10_stack.v
.............\pic10_status_reg.v
.............\pic10_tris_reg.v
.............\pic10_tri_state_port.v
.............\pic10_w_reg.v
.............\readme.txt
.............\test_pic10_alu.vt
.............\test_pic10_alu_datapath.vt
.............\test_pic10_alu_mux.vt
.............\test_pic10_cpu.vt
.............\test_pic10_ir.vt
.............\test_pic10_pc_datapath.vt
.............\test_pic10_ram_registers.vt
.............\test_pic10_ram_sfr_datapath.vt
.............\test_pic10_stack.vt
.............\test_pic10_status_reg.vt
.............\test_pic10_tri_state_port.vt
.............\test_pic10_tri_state_port2.vt
.............\test_pic10_w_reg.vt
pic10_verilog

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