Integrated RISC-CPU chip design, very practical program, beginner FPGA classmates help Austrian

彭岱的RISC --8\alu.v
..............\basic.rom
..............\cpu.v
..............\cpu_test.v
..............\cpu_test.v.bak
..............\dram.v
..............\exp.v
..............\idec.v
..............\pram.v
..............\r8.cr.mti
..............\r8.mpf
..............\r88.cr.mti
..............\r88.mpf
..............\regs.v
..............\risc8.cr.mti
..............\risc8.mpf
..............\risc8.vcd
..............\sindata.hex
..............\transcript
..............\vsim.wlf
..............\wave.do
..............\.ork\alu\verilog.asm
..............\....\...\_primary.dat
..............\....\...\_primary.vhd
..............\....\cpu\verilog.asm
..............\....\...\_primary.dat
..............\....\...\_primary.vhd
..............\....\..._test\verilog.asm
..............\....\........\_primary.dat
..............\....\........\_primary.vhd
..............\....\dram\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\exp\verilog.asm
..............\....\...\_primary.dat
..............\....\...\_primary.vhd
..............\....\idec\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\pram\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\regs\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\_info
..............\....\alu
..............\....\cpu
..............\....\cpu_test
..............\....\dram
..............\....\exp
..............\....\idec
..............\....\pram
..............\....\regs
..............\....\_temp
..............\work
彭岱的RISC --8

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