Introduction - If you have any usage issues, please Google them yourself
To complete the task of the experiment is to design a frequency meter, the system clock select core board 50MHz clock, the gate time is 1s (system clock divider), at the gate during the high input frequency counted, recorded when the gate goes low when the current value of the frequency and the frequency counter is cleared, the frequency display every two seconds to refresh. Measured frequency via a toggle switch to select the digital clock source module using the system clock signal from an external digital signal input through the input end of the system' s input and output modules for frequency measurement. When the toggle switch is high, the module of the digital signal of the digital clock signal of the measurement system, otherwise the measurements input from the outside, the digital signal.