Based on the IP core of FPG, realize FIR filter design

signal fir
..........\db
..........\..\altsyncram_kv91.tdf
..........\..\cmpr_vdg.tdf
..........\..\cntr_p9f.tdf
..........\..\fir.cbx.xml
..........\..\fir.cmp.rdb
..........\..\fir.db_info
..........\..\fir.eco.cdb
..........\..\fir.hif
..........\..\fir.map.qmsg
..........\..\fir.map_bb.hdb
..........\..\fir.sld_design_entry.sci
..........\..\fir.smart_action.txt
..........\..\fir.tis_db_list.ddb
..........\..\logic_util_heursitic.dat
..........\..\mux_frc.tdf
..........\..\mux_irc.tdf
..........\..\prev_cmp_fir.map.qmsg
..........\..\prev_cmp_fir.qmsg
..........\drom.bsf
..........\drom.cmp
..........\drom.v
..........\drom_bb.v
..........\drom_wave0.jpg
..........\drom_waveforms.html
..........\fir.asm.rpt
..........\fir.done
..........\fir.fit.rpt
..........\fir.fit.smsg
..........\fir.fit.summary
..........\fir.flow.rpt
..........\fir.map.rpt
..........\fir.map.smsg
..........\fir.map.summary
..........\fir.pin
..........\fir.qpf
..........\fir.qsf
..........\fir.qws
..........\fir.sta.rpt
..........\fir.sta.summary
..........\fir.v
..........\fir.v.bak
..........\fir1.html
..........\fir1.qip
..........\fir1.v
..........\fir1.vec
..........\fir1_ast.vhd
..........\fir1_ast.vhd.bak
..........\fir1_bb.v
..........\fir1_coef_int.txt
..........\fir1_constraints.tcl
..........\fir1_input.txt
..........\fir1_mlab.m
..........\fir1_model.m
..........\fir1_msim.tcl
..........\fir1_nativelink.tcl
..........\fir1_param.txt
..........\fir1_silent_param.txt
..........\fir1_st.v
..........\fir_assignment_defaults.qdf
..........\incremental_db
..........\..............\compiled_partitions
..........\..............\README
..........\sinwave.mif
..........\sinwave.v
..........\tb_fir1.vhd
..........\velocity.log

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