This is the default CPLD design shipped with the board. The CPLD helps reduce the number of jumpers on the board and simplifies the interaction of all the possible FPGA configuration memory sources

b-Xilinx CoolRunner-II CPLD\Nuevo Documento de Microsoft Office Word.docx
...........................\s3esk_cpld_design.zip
b-Xilinx CoolRunner-II CPLD

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